Mark G. Harward

Memory based digital signal processing

A cost-effective approach to increasing the processing throughput of many digital signal processing (DSP) systems is described.. This movement is achieved by migrating some of the basic computational elements to memory. The classic Von Neumann bottleneck is circumvented by localizing the computations to memory, and a high throughput is achieved by exploiting the memory architecture. For certain DSP applications that require a simple type of operation to be applied to a large amount of data, e.g. pattern recognition or matrix-matrix multiplications, the increase in throughput is very high. It is also shown that a system built with these memories is easier to use than systolic arrays or multiprocessor systems. As examples, compared to conventional solutions, a 10* improvement is shown for a continuous speech recognizer and a 16* improvement for a 128*128 matrix multiplication. Higher-orders-of-magnitude improvements are possible for larger problems and more memory chips.<<ETX>>

Approximate computation of signal characteristics of on-chip RC interconnect trees

Fast and efficient computation of signal characteristics such as delay, slew etc. play a key role in design and analysis of high performance VLSI circuits. Elmore approximation may not be accurate when resistive components of the interconnect significantly affect signal characteristics. An efficient mechanism to compute the driving point admittance of a resistive interconnect tree exists, in which the tree is traversed bottom-up to compute the driving point admittance (DPA). An approximation technique is proposed in this paper which involves traversing an interconnect RC tree top-down to compute the signal characteristics, by exploiting already calculated admittance at every node. A piecewise linear approximation obtained from the analytical expression for voltage at every node is used to compute voltages at subsequent nodes in the tree. The advantage of the proposed technique is efficient and fast computation of interconnect signal characteristics from already computed admittance information. Results comparing the proposed technique with RICE and Elmore on representative RC trees of antifuse based FPGA interconnect are presented.<<ETX>>

Process windows for convenient in-process monitoring of oxide and polysilicon etches

Process monitor window test structures are developed to standardize and to facilitate the in-process monitoring of oxide and polysilicon etches. With training, the operator can easily monitor and tune the etching process visually using these process windows. If a standard set of process monitor structures is developed for each technology and placed on all reticle sets using that technology, operators are provided with an easily recognized place to make their measurements. These windows standardize the measurement taking process, thereby reducing errors and improving quality.<<ETX>>

Field-Programmable Gate Arrays

A flexible FPGA logic module circuit includes a first logic circuit (12) for receiving a first plurality of input signals (14) and generating a first logic output signal (36) in response to the first plurality of input signals (14). A second logic circuit (24) for receiving a second plurality of FPGA logic modules (26, 28, 30, 54) for receiving a second plurality of input signals (44, 46, 48, 50, 52, 56, 64, and 66) and generating a second logic output signal (62) in response to the second plurality of input signals (44, 46, 48, 50, 52, 56, 64, and 66). Control circuitry (18) associates the first logic circuit (12) and the second logic circuit (24) to receive a wide plurality of input signals (14, and 44, 46, 48, 50, 52, 56, 64, and 66). The first logic circuit (12) receives certain first ones (14) of said wide plurality of input signals and the second logic circuit (24) receives certain second ones of the wide plurality of input signals (44, 46, 48, 50, 52, 56, 64, and 66). The control circuitry (18) further associates the first logic circuit (12) and the second logic circuit (24) to produce a single logic output (62) from the wide plurality of input signals (14, and 44, 46, 48, 50, 52, 56, 64, and 66).

A note on designing a comprehensive scanning electron microscopy test structure (for VLSI)

The authors have developed a family of computer generated test structures for scanning electron microscopy (SEM) sectioning. These test structures were designed to provide maximum topography and design rule process data with minimum sample preparation. The test structures were designed to be large enough to allow cleaving through the structures. The individual layout geometries were repeated in a staggered fashion across the structure to maximize the probability that a cleave will not require multiple passes of polishing to locate the position of interest. All the SEM structures were placed together so that a single sample makes all included physical parameters observable.<<ETX>>