David de Andrés

INERTE: integrated nexus-based real-time fault injection tool for embedded systems

Software implemented fault injection techniques (SWIFI) enable emulation of hardware and software faults. This emulation can be based on debugging mechanisms of general purpose processors [1] or in special debugging ports of embedded processors [2]. A well-known drawback of existing SWIFI tools rely on the temporal overhead introduced in the target system. This overhead is a problem when validating real-time systems. This paper presents a new SWIFI tool (INERTE) that solves this problem by using a standard debug interface called Nexus [3]. Using Nexus, system memory can be accessed at runtime without any intrusion in the target system. Thus, INERTE is able to inject transient faults without any temporal overhead.

Towards benchmarking routing protocols in wireless mesh networks

Wireless mesh networks (WMNs) establish a new, quick and low-cost alternative to provide communications when deploying a fixed infrastructure that could result prohibitive in terms of either time or money. During last years, the specification of multi-hop routing protocols for WMNs has been promoted, leading to their recent exploitation in commercial solutions. The selection of routing protocols for integration in WMNs requires the evaluation, comparison and ranking of eligible candidates according to a representative set of meaningful measures. In this context, the development of suitable experimental techniques to balance different features of each protocol is an essential requirement. This paper copes with this challenging task by proposing a benchmarking methodology to experimentally evaluate and compare the behaviour of these protocols. The feasibility of the proposed approach is illustrated through a simple but real (non-simulated) case study and reflects to what extent this methodology can be useful in increasing our knowledge on how real WMNs behave in practice.

Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems

Advances in circuitry integration increase the probability of occurrence of transient faults in VLSI systems. A confident use of these systems requires the study of their behaviour in the presence of such faults. This study can be conducted using model-based fault injection techniques. In that context, field-programmable gate arrays (FPGAs) offer a great promise by enabling those techniques to execute models faster. This paper focuses on how run-time reconfiguration techniques can be used for emulating the occurrence of transient faults in VLSI models. Although the use of FPGAs for that purpose has been restricted so far to the well-known bit-flip fault model, recent studies in fault representativeness point out the need of considering a wider set of faults modelling aspects like delays, indeterminations and pulses. Therefore, the main goal of this study is to analyse the different alternatives that FPGAs offer for the emulation of these faults while greatly decreasing the time devoted to models execution

An Attack Injection Approach to Evaluate the Robustness of Ad Hoc Networks

Ad hoc networks constitute a quick and cheap alternative to provide communications when deploying a fixed infrastructure could result prohibitive in terms of either time or money. Although the unique properties of ad hoc networks make them very sensitive to malicious faults attacks), most of current research has focused on improving their routing capabilities, thus widening their application domains, and very little attention has been devoted to their dependability. Accordingly, the confident use of this technology requires the development of new techniques and tools to assess the robustness of such networks in presence of attacks. This paper deals with this challenging goal by proposing an attack injection approach based on real ad hoc networks as experimental platform. Experiments show the feasibility of the proposed approach and identify a large number of possibilities to increase our knowledge on how real ad hoc networks behave in practice.

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification

Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated to the certification against the ISO26262 safety standard must be kept low for economical reasons. In this context, simulation-based verification using instruction set simulators (ISS) arises as a promising approach to partially cope with the increasing cost of the verification process as it allows taking design decisions in early design stages when modifications can be performed quickly and with low cost. However, it remains to be proven that verification in those stages provides accurate enough information to be used in the context of automotive microcontrollers. In this paper we analyze the existing correlation between fault injection experiments in an RTL microcontroller description and the information available at the ISS to enable accurate ISS-based fault injection.

A survey of evaluation platforms for ad hoc routing protocols

Routing protocols allow for the spontaneous formation of wireless multi-hop networks without dedicated infrastructure, also known as ad hoc networks. Despite significant technological advances, difficulties associated with the evaluation of ad hoc routing protocols under realistic conditions, still hamper their maturation and significant roll out in real world deployments. In particular, the resilience evaluation of ad hoc routing protocols is essential to determine their ability of keeping the routing service working despite the presence of changes, such as accidental faults or malicious ones (attacks). However, the resilience dimension is not always addressed by the evaluation platforms that are in charge of assessing these routing protocols.In this paper, we provide a survey covering current state-of-the-art evaluation platforms in the domain of ad hoc routing protocols paying special attention to the resilience dimension. The goal is threefold. First, we identify the most representative evaluation platforms and the routing protocols they have evaluated. Then, we analyse the experimental methodologies followed by such evaluation platforms. Finally, we create a taxonomy to characterise txperimental properties of such evaluation platforms.

On Selecting Representative Faultloads to Guide the Evaluation of Ad Hoc Networks

Ad hoc networks are threatened by a wide variety of accidental and malicious faults. This fact limits the practical exploitation of ad hoc networks. In consequence, apart from enforcing the dependability and security aspects of these networks, the provision of approaches to evaluate their behaviour in the presence of faults and attacks is of paramount importance. Accordingly, analysing and determining which threats should be considered for the evaluation of each particular ad hoc network is an essential task for the definition of representative faultloads. Our previous work focused on evaluating the impact of black and grey hole attacks in real networks using attack injection. This paper enriches the faultload of our experimental platform with five new types of accidental and malicious faults. The goal is to provide the basis for guiding the selection of suitable faultloads when assessing the impact of different threats in different types of ad hoc networks, like wireless sensor networks (WSN) and mobile ad hoc networks (MANET), considering the importance of the applicative context in the interpretation of results.

Using Dependability, Performance, Area and Energy Consumption Experimental Measures to Benchmark IP Cores

The selection of IP cores for integration in hardware systems requires the evaluation, comparison and ranking of all eligible core candidates. In this context, the development of suitable benchmarking techniques to balance the different performance, dependability, area and energy consumption measures is an essential, but also a challenging task. This paper specifies a benchmarking approach that exploits the capabilities of hardware prototyping tools to support system integrators in the selection of IP Cores. The goal is to enable the benchmarking of such cores in the early system design phases, as soon as their models can be synthesised on reconfigurable devices. Results show the feasibility of the approach and provide a taste of the kind of comparison and selection process supported by the benchmark.

The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs

Current integration scales are increasing the number and types of faults that embedded systems must face. Traditional approaches focus on dealing with those transient and permanent faults that impact the state or output of systems, whereas little research has targeted those faults being logically, electrically or temporally masked -which we have named fugacious. A fast detection and precise diagnosis of faults occurrence, even if the provided service is unaffected, could be of invaluable help to determine, for instance, that systems are currently under the influence of environmental disturbances like radiation, suffering from wear-out, or being affected by an intermittent fault. Upon detection, systems may react to adapt the deployed fault tolerance mechanisms to the diagnosed problem. This paper explores these ideas evaluating challenges and requirements involved, and provides an outline of potential techniques to be applied.

Attack Injection to Support the Evaluation of Ad Hoc Networks

The increasing emergence of mobile computing devices seamlessly providing wireless communication capabilities opens a wide range of new application domains for ad hoc networks. However, the sensitivity of ad hoc routing protocols to malicious faults (attacks) limits in practice their confident use in commercial products. This requires not only practical means to enforce the security of these protocols, but also approaches to evaluate their behaviour in the presence of attacks. Our previous contribution to the evaluation of ad hoc networks has been focused on the definition of an approach for injecting grey hole attacks in real (non-simulated) ad hoc networks. This paper relies on the use of this methodology to evaluate (i) three different implementations of a proactive ad hoc routing protocol, named OLSR, and (ii) two ad hoc routing protocols of different nature, one proactive (OLSR) and one reactive (AODV). Reported results have proven useful to extend the applicability of attack injection methodologies for evaluation beyond the mere assessment of the robustness of ad hoc routing protocols.