Juan Carlos Ruiz

Non-intrusive Software-Implemented Fault Injection in Embedded Systems

Critical embedded systems, like those used in avionics or automotive, have strong dependability requirements and most of them must face with fault tolerance. One of the methods typically used to validate fault tolerance mechanisms is fault injection. The idea is to study the behavior of the system in presence of faults in order to determine whether the system behaves properly or not. Software-implemented fault injection (SWIFI) techniques enable fault injection to be performed by software. Although interesting, major drawbacks of existing SWIFI techniques are the temporal and the spatial overheads they induced in the systems under study. The reduction of these overheads is thus crucial, in order to be confident on the results and conclusions of a SWIFI experiment. This paper focuses on this problem. It proposes a new non-intrusive SWIFI technique for injecting faults in embedded (system-on-chip) applications. The technique exploits the features of a standard debugging interface for embedded systems, called Nexus, in order to inject faults without temporal overhead. Then, Nexus features are also exploited in order to observe, without spatial intrusion, the behavior of the target system in presence of the injected faults. In other words, the embedded system under study can be controlled (for injecting faults) and observed (for tracing its behavior) without customizing its original structure or altering its normal execution. Since based on Nexus, the technique has also the benefit of being applicable to any Nexus-compliant system. In order to illustrate the potentials of the approach, we use an automotive embedded control unit application as a case study. Some preliminary results obtained from the experiments performed are also discussed.

Towards benchmarking routing protocols in wireless mesh networks

Wireless mesh networks (WMNs) establish a new, quick and low-cost alternative to provide communications when deploying a fixed infrastructure that could result prohibitive in terms of either time or money. During last years, the specification of multi-hop routing protocols for WMNs has been promoted, leading to their recent exploitation in commercial solutions. The selection of routing protocols for integration in WMNs requires the evaluation, comparison and ranking of eligible candidates according to a representative set of meaningful measures. In this context, the development of suitable experimental techniques to balance different features of each protocol is an essential requirement. This paper copes with this challenging task by proposing a benchmarking methodology to experimentally evaluate and compare the behaviour of these protocols. The feasibility of the proposed approach is illustrated through a simple but real (non-simulated) case study and reflects to what extent this methodology can be useful in increasing our knowledge on how real WMNs behave in practice.

Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems

Advances in circuitry integration increase the probability of occurrence of transient faults in VLSI systems. A confident use of these systems requires the study of their behaviour in the presence of such faults. This study can be conducted using model-based fault injection techniques. In that context, field-programmable gate arrays (FPGAs) offer a great promise by enabling those techniques to execute models faster. This paper focuses on how run-time reconfiguration techniques can be used for emulating the occurrence of transient faults in VLSI models. Although the use of FPGAs for that purpose has been restricted so far to the well-known bit-flip fault model, recent studies in fault representativeness point out the need of considering a wider set of faults modelling aspects like delays, indeterminations and pulses. Therefore, the main goal of this study is to analyse the different alternatives that FPGAs offer for the emulation of these faults while greatly decreasing the time devoted to models execution

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification

Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated to the certification against the ISO26262 safety standard must be kept low for economical reasons. In this context, simulation-based verification using instruction set simulators (ISS) arises as a promising approach to partially cope with the increasing cost of the verification process as it allows taking design decisions in early design stages when modifications can be performed quickly and with low cost. However, it remains to be proven that verification in those stages provides accurate enough information to be used in the context of automotive microcontrollers. In this paper we analyze the existing correlation between fault injection experiments in an RTL microcontroller description and the information available at the ISS to enable accurate ISS-based fault injection.

A survey of evaluation platforms for ad hoc routing protocols

Routing protocols allow for the spontaneous formation of wireless multi-hop networks without dedicated infrastructure, also known as ad hoc networks. Despite significant technological advances, difficulties associated with the evaluation of ad hoc routing protocols under realistic conditions, still hamper their maturation and significant roll out in real world deployments. In particular, the resilience evaluation of ad hoc routing protocols is essential to determine their ability of keeping the routing service working despite the presence of changes, such as accidental faults or malicious ones (attacks). However, the resilience dimension is not always addressed by the evaluation platforms that are in charge of assessing these routing protocols.In this paper, we provide a survey covering current state-of-the-art evaluation platforms in the domain of ad hoc routing protocols paying special attention to the resilience dimension. The goal is threefold. First, we identify the most representative evaluation platforms and the routing protocols they have evaluated. Then, we analyse the experimental methodologies followed by such evaluation platforms. Finally, we create a taxonomy to characterise txperimental properties of such evaluation platforms.

The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs

Current integration scales are increasing the number and types of faults that embedded systems must face. Traditional approaches focus on dealing with those transient and permanent faults that impact the state or output of systems, whereas little research has targeted those faults being logically, electrically or temporally masked -which we have named fugacious. A fast detection and precise diagnosis of faults occurrence, even if the provided service is unaffected, could be of invaluable help to determine, for instance, that systems are currently under the influence of environmental disturbances like radiation, suffering from wear-out, or being affected by an intermittent fault. Upon detection, systems may react to adapt the deployed fault tolerance mechanisms to the diagnosed problem. This paper explores these ideas evaluating challenges and requirements involved, and provides an outline of potential techniques to be applied.

From Measures to Conclusions Using Analytic Hierarchy Process in Dependability Benchmarking

Dependability benchmarks are aimed at comparing and selecting alternatives in application domains where faulty conditions are present. However, despite its importance and intrinsic complexity, a rigorous decision process has not been defined yet. As a result, benchmark conclusions may vary from one evaluator to another, and often, that process is vague and hard to follow, or even nonexistent. This situation affects the repeatability and reproducibility of that analysis process, making difficult the cross-comparison of results between works. To mitigate these problems, this paper proposes the integration of the analytic hierarchy process (AHP), a widely used multicriteria decision-making technique, within dependability benchmarks. In addition, an assisted pairwise comparison approach is proposed to automate those aspects of AHP that rely on judgmental comparisons, thus granting consistent, repeatable, and reproducible conclusions. Results from a dependability benchmark for wireless sensor networks are used to illustrate and validate the proposed approach.

Mitigating the impact of ambient noise on Wireless Mesh Networks using adaptive link-quality-based packet replication

Wireless Mesh networks (WMN) typically rely on proactive routing protocols to establish optimal communication routes between every pair of system nodes. These protocols integrate link-quality-based mechanisms to minimise the adverse effect of ambient noise on communications. This paper shows the limitations existing in such mechanisms by analysing the impact of ambient noise on three state-of-the-art proactive routing protocols: OLSR, B.A.T.M.A.N and Babel. As will be shown, the lack of context-awareness in their link-quality mechanisms prevents the protocols from adjusting their behaviour according to persistent levels of ambient noise, which may vary along the time. Consequently, they cannot minimise the impact of such noise on the availability of network routes. This issue is very serious for a WMN since the loss communication links may strongly increase the convergence time of the network. An adaptive extension to studied link-quality-based mechanisms is proposed to avoid the loss of communication links in the presence of high levels of ambient noise. The effectiveness of the proposal is experimentally assessed, thus establishing a new method to reduce the impact of ambient noise on WMN.

REFRAHN: A Resilience Evaluation Framework for Ad Hoc Routing Protocols

Abstract Routing protocols are key elements for ad hoc networks. They are in charge of establishing routes between network nodes efficiently. Despite the interest shown by the scientific community and industry in converting the first specifications of ad hoc routing protocols in functional prototypes, aspects such as the resilience of these protocols remain generally unaddressed in practice. Tackling this issue becomes critical given the increasingly variety of accidental and malicious faults (attacks) that may impact the behaviour exhibited by ad hoc routing protocols. The main objective of this paper is to deepen in the methodological aspects concerning fault injection in routing protocols. As a result, we will design and implement a framework based on the injection of accidental and malicious faults to quantitatively evaluate their impact on routing protocols. This framework, called REFRAHN (Resilience Evaluation FRamework for Ad Hoc routiNg protocols), can be used to (i) reduce the uncertainty about the sources of perturbations in the deployment of ad hoc routing protocols, (ii) design fault-tolerant mechanisms that address and minimise such problems, and (iii) compare and select which is the routing protocol that optimises the performance and robustness of the network.

Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments

Field-Programmable Gate Arrays (FPGA) have proven their value over time as final implementation targets. Their singular architecture renders them sensitive to a wide range of faults, specially to those causing multiple and non-simultaneous errors, that can result in silent data corruption and also in structural changes in the hardware implementation. This papers presents and tests an approach to enable the confident use of conventional (low-cost) FPGAs in hostile environments. The design combines spatial and temporal redundancy with partial dynamic reconfiguration to increase the resilience of designs. The goal is to tolerate the occurrence of single and multiple faults, even during the reconfiguration process of FPGAs, while minimizing the impact of the recovery process on system availability. Fault injection techniques are used to experimentally evaluate various features of the approach. Results are very promising and lead us to state that, although many research is still required, the old idea of self-repairing HW designs is closer today.