David De Roest

Influence of the UV Cure on Advanced Plasma Enhanced Chemical Vapour Deposition Low-

In a recent study, low-k thin films with low dielectric constant (≤2.1) and high Youngs modulus (>5 GPa) were obtained by introducing a remote plasma step between the traditional plasma enhanced chemical vapour deposition and UV curing. This study shows that the UV curing step with a narrow band lamp with wavelength of 172 nm induced more network Si–O and Si–H bonds and more densification than the curing step with a broadband lamp with wavelengths higher than 200 nm. As a consequence, the dielectric constant of the narrow band cured film was slightly higher, but Youngs modulus and hardness were much improved. Electrical characterization showed good breakdown voltages and a more than sufficient time dependent dielectric breakdown reliability. The broadband lamp was then used to form thicker films which retained very well the characteristics of the thin films.

k

The dielectric reliability of Aurora® LK (k = 3.0) material has been evaluated on a 50 nm half pitch test structure. These were fabricated using a double patterning scheme and TiN metal hard mask. The introduction of a suitable post-etch residue removal step and close-coupled processing between Cu electroplating and chemical mechanical polishing were found to be key for achieving high yield. Median time-dependent dielectric lifetime of 10 years is reached at an electrical field of 1.4 MV/cm, comparable to earlier reported results with SiO2 as dielectric. The reliability performance is found to be significantly layout dependent with corners being weak points due to local field enhancement.

Materials

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.

Dielectric Reliability of 50 nm Half Pitch Structures in Aurora® LK

In this work, we explore the performances of a low-temperature PEALD technology used to trim/clean/smooth and reshape ArF photoresist lines that could subsequently receive an in-situ spacer deposition required to build up any SAxP grating. Different gas mixtures (O2, N2, H2, Ar and combinations) are evaluated on both blanket and patterned wafers. Trim rate, line profile, surface roughness and chemical modification are characterized using ellipsometry, Fourier transform infrared spectroscopy and atomic force microscopy. The photoresist line roughness is measured from top down SEM imaging and the different contributors to the roughness determined from a Power Spectral Density (PSD) analysis. Few results obtained on EUV photoresist blanket wafers using similar plasma treatments will also be briefly presented.

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora® LK HM

As dimension of bulk Si field-effect transistors scales down, novel techniques for impurity profile design at channel area are required because suppression of short-channel effects and improvement of on-state current is tradeoff in conventional ion implantation process. In this paper, we demonstrate p-type bulk Si fin field-effect transistors by using solid-source doping for better impurity profile in fin to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current. In this paper, impurity profiles in fin with two different kinds of anneal conditions after fin revelation (1000 °C 30 s and 1050 °C spike) are analyzed, and the better impurity profile at channel area is designed by 1000 °C 30-s anneal for better electrical characteristics. The anneal condition with the better impurity profile in fin showsmobility improvement at long gate length (

Exploration of a low-temperature PEALD technology to trim and smooth 193i photoresist

1~\mu \text{m}

The Improvement of Subthreshold Slope and Transconductance of p-Type Bulk Si Field-Effect Transistors by Solid-Source Doping

) and short gate lengths (60, 70, and 80 nm); subthreshold slope and transconductance are improved at the same time. With those results, we conclude that a fabrication process flow of p-type bulk Si fin field-effect transistors to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current is established with 1000 °C 30-s anneal after fin revelation by using solid-source doping. At the same time, electrical characteristics variation is also suppressed in the case of 1000 °C 30-s anneal.