Hessel Sprey

Development of sub-10-nm atomic layer deposition barriers for Cu/low-k interconnects

The development of atomic layer deposition (ALD) barriers with a thickness below 10 nm for copper/low-k dielectric interconnects was reviewed. The CMOS 65-nm technology node, which is presumably the first node, at which ALD barriers will be employed, was taken as a reference. The ALD barrier process will most likely meet the geometrical requirements, i.e. the capability to deposit barrier films in narrow dimensions. In order to establish the compliance of ALD barriers with the thickness requirements, the growth of the ALD layer was investigated. It was shown that the growth of the ALD films proceeds via islands, which are formed in the nucleation step. The thickness, which is necessary to close the surface of the substrate, depends on process conditions and barrier material. It is argued that the minimum barrier thickness should be at least of the same order as the thickness to achieve closure. In the 65-nm technology node barriers have to be compatible with low-k dielectric materials. To achieve growth of ALD barriers on dense low-k materials, surface treatments of the dielectric films have to be implemented. The deposition of ALD films on dielectric materials with an interconnected pore structure results in penetration of the ALD precursors into the pore system and deposition of the barrier inside the dielectric material.

Evaluation of integrity and barrier performance of atomic layer deposited WNxCy films on plasma enhanced chemical vapor deposited SiO2 for Cu metallization

The nucleation and growth of WNxCy films deposited by atomic layer deposition (ALD) on plasma enhanced chemical vapor deposited (PECVD) SiO2 is characterized as a function of the number of ALD cycles using transmission electron microscopy analysis. The island growth of isolated WNxCy nanocrystals is directly observed at the early stages of film growth. The nucleation of the WNxCy film can be significantly enhanced by NH3 plasma treatment before the deposition of WNxCy. The capacitance-voltage measurements conducted after bias-temperature stressing reveals that an ALD-WNxCy film deposited with a thickness of approximately 5.2nm on the NH3 plasma-treated PECVD SiO2 shows good diffusion barrier performance against Cu migration.

Impact of ALCVD and PVD Titanium Nitride Deposition on Metal Gate Capacitors

In this paper it will be shown that the deposition method is an important parameter for the electrical properties of the metal gate. Indeed, ALCVD(Atomic Layer Chemical Vapor Deposition) TiN metal has a 5.3eV workfunction, suitable for PMOS devices. The PVD sputtered (Physical Vapor Deposition) TiN has a lower workfunction around 4.8eV and is mid-gap like. The PVD TiN capacitors have a higher effective oxide charge than the ALCVD capacitors as extracted from capacitance measurements and from workfunction calculations. PVD TiN also exhibits process-induced damage as seen from leakage measurements.

Key factors to sustain the extension of a MHM-based integration scheme to medium and high porosity PECVD low-k materials

Interconnect solutions for advanced technology nodes using PECVD techniques for low-k deposition require the use of porogen-based process with post deposition UV cure. By using two different UV cure lamps (A, B) in combination with different porogen loads, three different micro-porous low-k films are developed: Aurora® ELK HM (k~2.5; porosity (P) ~25%), Aurora® ELK A (k~2.3; P~34%) and Aurora® ELK B (k~2.2; P~37%). Integrating these materials is complex and challenging. We discuss key factors that are instrumental to the extension of a metal hard mask (MHM)-based integration scheme to these 3 low-k films. Our findings: (I) for sub-100nm dimensions, patterning and low-k interactions affect the dynamic of organic residue formation and thereby impact electrical yield; (II) choosing the right ash, etch and clean sequence is mandatory to control plasma damage, profile, residues and corrosion on top of the MHM; (III) Cu reduction plasmas must be adjusted when porosity is increased to mitigate field damage.

Use of MIR-FTIR and k-value Measurements to Assess Potential Solutions to Reduce Damage During Porous Low-k Integration

Multiple Internal Reflection (MIR) FTIR is used to assess the impact of potentially damaging BEOL integration process steps such as Chemical Mechanical Polishing (CMP) and NH3-based plasmas on a k=2.55 porous interlayer dielectric. The NH3 plasma is found to be very damaging, and a He plasma prior to the same NH3 plasma leads to a damage reduction. The impact of CMP is also confirmed and leads to an equivalent k-value degradation as a He + NH3 plasma. In order to reduce the integration damage, the addition of a low-k protective cap layer (k=3.3) is proposed. The required thickness to avoid impact from CMP and NH3-based plasmas is found to be 10 nm after CMP (Kstack=2.60 with 10 nm cap). As a result, those process steps are no longer a concern with this integration route.

Integration of Porogen-Based Low-k Films: Influence of Capping Layer Thickness and Long Thermal Anneals on Low-k Damage and Reliability

This paper discusses integration aspects of a porous low-k film (k ~2.45) cured with a broadband UV lamp. Different process splits are discussed which could contribute to avoid integration induced damage and improve reliability. The main factor contributing to a successful integration is the presence of a thick (protecting) cap layer partially remaining after chemical mechanical polishing (CMP), which leads to yielding structures with a keff of ~2.6, a breakdown voltage of ~6.9 MV/cm and time dependent dielectric breakdown (TDDB) lifetimes in the excess of 100 years. Long thermal anneals restore the k-value but degrade lifetime.

Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node

Single damascene (SD) Cu/Aurorareg ULK interconnects with a minimum spacing of 50nm are achieved by using a metal hard mask (MHM) integration scheme, which enables to perform the resist ash before dielectric etch. This patterning scheme is used in combination with a low damage etch technique based on sidewall protection. Interconnect performance and reliability can be further improved by using Aurorareg ULK high modulus (HM), a low-k film with a reduced diffusivity as compared to Aurora ULK, and a comparable k-value of 2.7. The MHM approach results in a limited increase in integrated k-value by 0.1 for ULK HM vs. 0.3 for Aurorareg ULK. The median time dependent dielectric breakdown (TDDB) lifetime is well above the 10 years criterion for spacings down to the 50nm. Finally, the MHM integration scheme enabled fabrication of dual damascene interconnects with Aurorareg ULK HM