Jan Willem Maes

Remote-charge-scattering limited mobility in field-effect transistors with SiO2 and Al2O3∕SiO2 gate stacks

We examined, both experimentally and theoretically, the mobility reduction in metal-insulator-semiconductor field-effect transistors (MISFETs) limited by remote charge scattering. The accuracy of the mobility calculations was confirmed by agreement with experiments on MISFETs with pure SiO2 gate dielectrics, in which mobility is reduced due to scattering from the depletion charges in the polycrystalline silicon gate. In MISFETs with Al2O3∕SiO2 gate stacks, we could not identify the contributions from the remote phonon scattering by using low-temperature measurements of the mobility. The experimental mobility reduction is explained by a model in which both negative and positive charges are located at the Al2O3∕SiO2 interface. According to this model, the mobility increases with the interfacial SiO2 thickness. We confirmed this by fabricating MISFETs with various interfacial SiO2 thicknesses.

Tailoring switching and endurance / retention reliability characteristics of HfO 2 / Hf RRAM with Ti, Al, Si dopants

We have demonstrated that by material engineering using different spices to dope HfO2, RRAM cell switching and endurance / retention reliability characteristics can be modulated. The changes in SET/RESET voltages, endurance optimal programming window and retention result mainly from the oxygen scavenging efficiency of Hf cap in presence of different dopants in HfO2. This impacts directly the formation of OEL that controls the RRAM switching characteristics and retention. By utilizing different dopant materials, the operation range of the HfO2 based RRAM can be tailored to be compatible with different selectors and to be adopted for broader applications.

Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps

This paper presents a detailed investigation of the temperature dependence of frequency dispersion observed in capacitance-voltage (C-V) measurements of III-V metal-oxide-semiconductor (MOS) devices. The dispersion in the accumulation region of the capacitance data is found to change from 4%–9% (per decade frequency) to ∼0% when the temperature is reduced from 300 K to 4 K in a wide range of MOS capacitors with different gate dielectrics and III-V substrates. We show that such significant temperature dependence of C-V frequency dispersion cannot be due to the temperature dependence of channel electrostatics, i.e., carrier density and surface potential. We also show that the temperature dependence of frequency dispersion, and hence, the capture/emission process of border traps can be modeled by a combination of tunneling and a “temperature-activated” process described by a non-radiative multi-phonon model, instead of a widely believed single-step elastic tunneling process.

Impact of sequential infiltration synthesis on pattern fidelity of DSA lines

Numerous block copolymer (BCP) systems can be used in directed self-assembly (DSA) processes to form patterns useful in lithography, especially lines and spaces with lamellar phase systems and vias/pillars with cylindrical phase systems. However, most of these BCP systems with attractive pattern formation capabilities have limited plasma etch contrast between the polymer domains. One potential solution to greatly enhance this etch contrast is a recently developed technique called sequential infiltration synthesis (SIS). SIS is a self-limiting synthesis technique, like atomic layer deposition, where organometallic (OM) precursor vapours and oxidants are introduced into self-assembled block copolymer systems in multiple cycles. In the first half of each cycle the OM precursor selectively reacts with one polymer domain, and in the second half of the cycle the oxidant reacts with the OM groups in the polymer film to selectively form metallic compounds in one of the polymer domains. Thus, the polymer pattern is transformed into a metallic mask with much enhanced plasma etch contrast. We report the effects of such a block-selective SIS process of metallic compounds on the feature sizes, roughness and profiles of patterns formed with BCP systems.

The mechanism of mobility degradation in MISFETs with Al/sub 2/O/sub 3/ gate dielectric

We believe that the most important task in the development of high-/spl kappa/ gate dielectrics is to engineer the interface to assure high enough mobility and reliability. Considering the 100-nm node, Al/sub 2/O/sub 3/ would appear to be the most promising candidate in terms of chemical and thermal stability, barrier offset, and compatibility with the conventional CMOS process. The integration of Al/sub 2/O/sub 3/ gate dielectrics in sub-100 nm-FETs has already been demonstrated; however, the resulting electron mobility was only a quarter the value for a FET with SiO/sub 2/ gate dielectric (D. Buchanan et al., Tech. Digest IEDM, p. 223, 2000; J.H. Lee et al., ibid., p. 645, 2000). We have clarified the mechanism by which mobility is thus degraded, both experimentally and theoretically.

Atomic Layer Deposition: An Enabling Technology for Microelectronic Device Manufacturing

Atomic layer deposition (ALD) recently emerged as an enabling technology for microelectronic device fabrication. This technique provides the unique capability to deposit ultra thin films with the thickness control, uniformity, step coverage, and electrical/mechanical properties required to support device manufacturing at the 45 nm node and beyond. This paper will review the fundamentals of ALD processing and describe the equipment used. Applications of ALD in the fabrication of advanced gate stacks, on-chip capacitors, and thin film magnetic heads are presented.

Improved cost-effectiveness of the block co-polymer anneal process for DSA

This manuscript first presents a cost model to compare the cost of ownership of DSA and SAQP for a typical front end of line (FEoL) line patterning exercise. Then, we proceed to a feasibility study of using a vertical furnace to batch anneal the block co-polymer for DSA applications. We show that the defect performance of such a batch anneal process is comparable to the process of record anneal methods. This helps in increasing the cost benefit for DSA compared to the conventional multiple patterning approaches.

First demonstration of ∼3500 cm 2 /V-s electron mobility and sufficient BTI reliability (max V ov up to 0.6V) In 0.53 Ga 0.47 As nFET using an IL/LaSiO x /HfO 2 gate stack

In this paper, we demonstrate for the first time an implant free In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V<inf>ov</inf> of 0.6 V. In addition, an excellent electron mobility (μ<inf>eff, peak</inf>=3531 cm2/V-s), low SS<inf>lin</inf>=71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance, reliability and further reduction of the sub-threshold swing (SS<inf>lin</inf>=68mV/dec). On top of the novel IL we presented last year, in this paper we insert a LaSiO<inf>x</inf> layer between the IL and HfO<inf>2</inf> offering an increased chemical stability of the gate stack. This combination is key and offers both an improved interface quality as well as a reduction of the oxide trap density.

Catalyst Assisted Low Temperature Pre Epitaxial Cleaning for Si and SiGe Surfaces

Novel scaling approaches such as sGe channels on strain relaxed SiGe buffers, source/drain (S/D) stressors for FINFETs are usually grown using epitaxial process. Prior to the epitaxial growth, the starting surface should be free from oxygen and organic impurities. If not, these impurities would act as nucleating centres for defect formation resulting in defective epi growth. Conventionally, the wafers are HF dipped and then subjected to in-situ hydrogen bake at a temperature of 800°C in order to remove the above said impurities present on the wafer surface [1]. However, subjecting the strain relaxed SiGe to such high temperature baking would lead to roughening/islanding and subjecting the fins to high temperature baking might result in severe surface reflow [2]. As a result, the device performance would be adversely affected.

Innovative thin film deposition technologies enabling new materials and new device integration roadmaps

Innovative thin film deposition technologies play a key role in new device scaling strategies that are increasingly based on the use of new materials and 3D approaches. Smart tailor-made equipment solutions have enabled processes that were previously considered impossible for volume manufacturing. Examples of atomic layer deposition and epitaxy techniques for logic and memory devices will be presented as well as spin-offs to applications in solar cells and hard disks.