David Guevorkian

Low-power application-specific FFT processor for LTE applications

In this paper, we describe a processor architecture tailored to mixed-radix4/2/3 FFT algorithm. The proposed design supports all FFT sizes, namely 128-2048/1536, required by the LTE applications. The processor is based on the Transport Triggered Architecture processor architecture, which was customized with a set of function units, designed especially for the application at hand. The processor has been synthesized on an ASIC technology and both energy-efficiency and performance have been evaluated. The developed processor is programmable but shows energy-efficiency comparable to fixed-function ASIC implementations.

Pipelined FFT for wireless communications supporting 128–2048 / 1536 -point transforms

Modern wireless communication systems use orthogonal frequency division multiplexing (OFDM) and multiple input multiple output (MIMO) schemes, which call for fast Fourier transforms (FFT). Traditionally power-of-two FFT lengths have been exploited but recently also non-power-of-two transform lengths have been defined. For example, 3GPP LTE specification defines 1536- point FFT. In this paper, we propose a pipeline FFT architecture, which supports FFT lengths of power-of-two multiple of three. The architecture is basically single delay feedback structure followed by radix-3 computation unit. The proposed architecture is memory optimal as for N-point transform only N - 1 memory locations are needed.

Guest Editorial: Special Issue on Embedded Computer Systems: Architectures, Modeling and Simulation

This special edition of IJPP includes extended journal versions of the five best papers from the 2012 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XII). The five papers were selected from 27 high quality papers presented at the conference, which had an overall acceptance rate of 40 %. Held in Agios Konstantinos, Samos, Greece from 16th to 19th July 2012, SAMOS (http://www.samos-conference.com) is a unique annual event on embedded computing systems, bringing together researchers from industry and academic in a uniquely relaxing atmosphere which combines dissemination of state-of-the-art research with afternoon beach and boat trips and day-long hikes in the mountains, all bathed in the glorious sunshine of Samos in July. In every sense of the word, SAMOS is a unique event. The first article included, ‘Low-Power Reconfigurable Miniature Sensor Nodes for Condition Monitoring’ the authors describe a reconfigurable sensor node realised on a Flash Field Programmable Gate Array (FPGA) using a Transport Triggered Architecture (TTA). This architecture enables unique floating-point arithmetic support, with highly competitive power consumption statistics.

Circulant Hermitian Matrix Inversion Method Based on Discrete Cosine and Sine Transforms

A novel fast method for finding the inverse of a circulant Hermitian matrix is proposed. Inversion of such matrices is one of the most computationally complicated steps in many algorithms of communication technologies, signal processing, and other fields. The proposed method is based on using Discrete Cosine (DCT-1) and Discrete Sine (DST-1) transforms of Type 1. It reduces the number of operations approximately by a factor of four compared to conventional Fast Fourier Transform (FFT) based method.