Ville Lappalainen

Complexity of optimized H.26L video decoder implementation

An analysis of computational complexity is presented for an H.26L video decoder, based on extensive experiments on a general-purpose processor. In addition, platform-independent techniques to optimize an H.26L decoder implementation are given. Comparisons are carried out between our highly optimized version of H.26L, the public reference implementation of H.26L, and a highly optimized H.263+ implementation. Both QCIF and CIF-sized image sequences are used. The results show that with equal visual quality, the bit-rate savings range from 28% to 58%, while the frame decoding speed of H.26L is about 11% better than that of a highly optimized H.263+.

Overview of research efforts on media ISA extensions and their usage in video coding

This paper summarizes the results of over 25 research groups or individual researchers that have presented video coding implementations on general-purpose processors with the new single instruction multiple data media instruction set architecture extensions. The extensions are introduced and the fundamentals for extensions, as well as some inherent problems, are explained. The reported attempts to utilize the extensions are divided into kernel- and application-level, as well as platform dependent and independent optimizations. Optimized applications include, in addition to some proprietary methods, all of the major video coding standards such as H.261, H.263, MPEG-4, MPEG-1, and MPEG-2. These optimized implementations include a complete video codec, several decoders, and several encoders. Additionally, a performance comparison is given for four representative encoder implementations based on the reported results. Also included is an overview of future trends for new instructions and architectural speed-up techniques.

Performance analysis of low bit rate H.26L video encoder

A new video encoder proposal, H.26L, is compared against H.263 and H.263+. In the comparison, both computational complexity and compression performance are analyzed. Moreover, the trade-off possibilities between the complexity and compression performance within H.26L are presented. Experimental comparisons with H.263 and H.263+ show that H.26L reduces the output bit rate about 30% with the same quality. The computation time increases about three times compared to H.263 and leads into the encoding speed of 3-6 fps for QCIF sequences on a 400 MHz Pentium III processor. Realtime operation can be achieved by applying additional, algorithmic and platform-specific optimizations.

Performance of H.26L video encoder on general-purpose processor

Two optimized implementations of the emerging ITU-T H.26L video encoder are described. The first, medium-optimized version, is implemented in C and the latter, highly optimized version, utilizes both algorithmic and platform-specific optimizations. Comparisons to a correspondingly optimized H.263/H.263+ implementation are given with the spatial and temporal video quality fixed and the bit rate and complexity varied. On a 733 MHz general-purpose processor, an average encoding speed of 17 frames per second for QCIF sequences is achieved with a 29% reduction in bit rate compared to H.263+. The complexity of H.26L is about 3.4 times more than that of H.263+.

Architectures for the sum of absolute differences operation

Efficient architectures for computing the sum of absolute differences (SAD) between two data sets are proposed in application to motion estimation in a mobile video coding system. The proposed architectures combine and further develop advantages of two earlier proposed architectures. As a result, higher performance is achieved despite the lower cost (gate count and power consumption) as compared to a conventional architecture. Proposed architectures are feasible for integrating into mobile video processing systems. They support not only regular, data independent motion estimation strategies but all of those based on the SAD criterion. Early termination mechanisms included into the proposed architecture allow one to avoid unnecessary computations which may often take place in conventional SAD architectures without such mechanisms.

Performance analysis of Intel MMX technology for an H.263 video H.263 video encoder

2. ~RODUCTION The htemationd Telecommunication Union, Telecommunication Standardisation Sector ~-~, has specified the first version of the H263 standard for video coding for low bit rate communication enabfing compression of video sequences to bit rates below @ kbps. The standard specifies a hybrid coding method containing discrete cosine transform @~ intra ties, and motion compznsatd and Da transformed inter frames. Applications for which tie standard is suitable include \<deo phone applications in the current Pubfic Switched Telephone Network &S~, and in future mobfie networks with data rates similar to the data rates of PS~. An H.263 encoder is one component of a video phone application.

Optimization of emerging H.26L video encoder

Two optimized implementations of the emerging ITU-T H.26L video encoder are described. The first, medium-optimized version, is implemented in C and the latter, highly optimized version, utilizes MMX assembly instructions. Comparisons to a correspondingly optimized H.263/H.263+ implementation are given with the spatial and temporal video quality fixed and the bit rate and complexity varied. On a 733 Pentium III processor, a real-time encoding speed of 10 fps for QCIF (quarter common intermediate format) sequences is achieved with a 29% reduction in bit rate compared to H.263+. The complexity of H.26L is about 3.4 times more than that of H.263+.

Experimental parallel implementation of a wavelet-based still image encoder

Abstract A still image encoder implementation is presented for a multi-DSP system called PARNEU, which has previously been developed for neural network and signal processing applications. The core of the implementation is based on experimental mappings of discrete wavelet transform (DWT) on the parallel processor architecture. PARNEU has a flexible interconnection network architecture with message passing, which allows adding more processing units (PUs) to the system whenever more computational power is needed. Program code can be written to adapt to the number of PUs. This is utilized in the presented encoder implementation with emphasis on load balancing among processors as well as on balance between communication and computation. Performance of the implementation is measured with a scaleable number of processors and compared to a sequential reference implementation. Results show that the DWT phase can be efficiently parallelized on PARNEU with 95.6% of its time spent on true parallel computation. The overall speedup with four processors is 2.25, which could be improved by further optimization of an adaptive scanning phase of the encoder.

A method for designing high-radix multiplier-based processing units for multimedia applications

Multifunctional architecture for video and image processing (MAVIP) to be used in multimedia systems are proposed. MAVIP is a family of reconfigurable architectures derived from a single high-radix (4, 8, or 16) multiplier structure where: a) the list of potential partial products obtained at the first stage of multiplication may be reused; b) pipeline stages may be parallelised at different level to achieve required clock frequency and to improve balancing between these stages; and c) interconnections between the operational blocks may be multiplexed to make the structure multifunctional and to allow reusing basic multiplier blocks. The same device may operate either as a programmable processing unit with digital signal processor-specific operations or as a reconfigurable ASIC. Being small, MAVIP indicates competitive performance in video coding applications.

Detecting corrupted intra macroblocks in H.263 video

Corrupted low frequency data of intra coded macroblocks can significantly degrade quality of video in error prone wireless networks. Therefore, a new method for detecting the corrupted blocks is presented. The method exploits temporal smoothness of video by computing the absolute difference between subsequent video frames. A threshold function is used to highlight the block differences, and a heuristic is developed to detect the corrupted blocks. The proposed method is evaluated with our wireless video simulator, which shows that the method substantially improves image quality of video conferencing sequences in presence of transmission errors. In addition, the method is compared to average intersample difference across the block boundaries (AIDB) algorithm whose performance is shown to be more sensitive to selection of correct threshold values than the proposed method.