David Hetzer

Fabrication of 28nm pitch Si fins with DSA lithography

Directed Self-Assembly (DSA), as an extension of current state-of-the-art photolithography, has demonstrated the capability for patterning with resolution and cost effectiveness beyond the capability of other techniques. Previous studies of DSA have reported encouraging benchmarks in defect density and throughput capability for the patterning step, and such results provide a foundation for our ongoing efforts to integrate the DSA patterning step into a robust process for fabricating device layers. Here we provide a status report on the integration of two chemoepitaxy DSA patterning methods for the fabrication of 28nm pitch Si fin arrays. In addition to the requirements for a robust pattern transfer process, it is also important to understand the pattern design limitations that are associated with DSA. We discuss some of the challenges and opportunities associated with developing efficient device designs that take advantage of the capabilities of DSA.

Directed self-assembly process implementation in a 300mm pilot line environment

The patterning capability of the directed self-assembly (DSA) of a 42nm-pitch block copolymer on an 84nm-pitch guiding pattern was investigated in a 300mm pilot line environment. The chemoepitaxy guiding pattern was created by the IBM Almaden approach using brush materials in combination with an optional chemical slimming of the resist lines. Critical dimension (CD) uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) of the DSA process were characterized. CD rectification and LWR reduction were observed. The chemical slimming process was found to be effective in reducing pattern collapse, hence, slightly improving the DSA PW under over-dose conditions. However, the overall PW was found to be smaller than without using the slimming, due to a new failure mode at under-dose region.

Manufacturability considerations for DSA

Implementation of Directed Self-Assembly (DSA) as a viable lithographic technology for high volume manufacturing will require significant efforts to co-optimize the DSA process options and constraints with existing work flows. These work flows include established etch stacks, integration schemes, and design layout principles. The two foremost patterning schemes for DSA, chemoepitaxy and graphoepitaxy, each have their own advantages and disadvantages. Chemoepitaxy is well suited for regular repeating patterns, but has challenges when non-periodic design elements are required. As the line-space polystyrene-block-polymethylmethacrylate chemoepitaxy DSA processes mature, considerable progress has been made on reducing the density of topological (dislocation and disclination) defects but little is known about the existence of 3D buried defects and their subsequent pattern transfer to underlayers. In this paper, we highlight the emergence of a specific type of buried bridging defect within our two 28 nm pitch DSA flows and summarize our efforts to characterize and eliminate the buried defects using process, materials, and plasma-etch optimization. We also discuss how the optimization and removal of the buried defects impacts both the process window and pitch multiplication, facilitates measurement of the pattern roughness rectification, and demonstrate hard-mask open within a back-end-of-line integration flow. Finally, since graphoepitaxy has intrinsic benefits in terms of design flexibility when compared to chemoepitaxy, we highlight our initial investigations on implementing high-chi block copolymer patterning using multiple graphoepitaxy flows to realize sub-20 nm pitch line-space patterns and discuss the benefits of using high-chi block copolymers for roughness reduction.

Towards electrical testable SOI devices using Directed Self-Assembly for fin formation

The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

SADP for BEOL using chemical slimming with resist mandrel for beyond 22nm nodes

The fundamental limits of optical lithography have driven semiconductor processing research to push the envelope. Double patterning (DP) techniques including litho-etch litho-etch (LELE), litho-litho etch (LLE), and self-aligned double patterning (SADP) have become standard vernacular for near term semiconductor processing as EUV is not yet ready for high volume production. The challenge, even with techniques like LLE and SADP, remains that printing small lines on tight pitches (for LLE) or even small lines on relaxed pitches for mandrel/spacer combinations is not trivial. We have demonstrated a track-based slimming technique that can produce sub-25 nm resist lines for either SADP or LLE DP processes. Our work includes results for varying shrink amounts at different target critical dimensions (CD) and for multiple pitches. We also investigated CD uniformity (CDU) and defectivity. In particular, optimization of the amount of slimming is critical as it allows for much greater process latitude at the lithography step. In addition to the lithography work, we have continued the processing for both integration schemes to include oxide deposition and etch for SADP and through etch performance for DP. We have demonstrated sub 45 nm pitch structures. The wide variety of process uses, as well as the ability to achieve a large range of shrink amounts shows that track based slimming is a viable solution to achieve target CD and pitch values for sub 22 nm technology node.

Towards manufacturing of advanced logic devices by double-patterning

As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

DSA patterning options for FinFET formation at 7nm node

Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.

DSA patterning options for logics and memory applications

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

DSA via hole shrink for advanced node applications

Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.