Akiteru Ko

Fabrication of 28nm pitch Si fins with DSA lithography

Directed Self-Assembly (DSA), as an extension of current state-of-the-art photolithography, has demonstrated the capability for patterning with resolution and cost effectiveness beyond the capability of other techniques. Previous studies of DSA have reported encouraging benchmarks in defect density and throughput capability for the patterning step, and such results provide a foundation for our ongoing efforts to integrate the DSA patterning step into a robust process for fabricating device layers. Here we provide a status report on the integration of two chemoepitaxy DSA patterning methods for the fabrication of 28nm pitch Si fin arrays. In addition to the requirements for a robust pattern transfer process, it is also important to understand the pattern design limitations that are associated with DSA. We discuss some of the challenges and opportunities associated with developing efficient device designs that take advantage of the capabilities of DSA.

Towards electrical testable SOI devices using Directed Self-Assembly for fin formation

The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.

Line width roughness control for EUV patterning

Controlling line width roughness (LWR) is a critical issue in extreme ultraviolet lithography (EUVL). High sensitivity, high resolution, and low LWR are required for EUV lithography resist. However, simultaneously achieving optimal properties through chemical tuning alone is difficult. The track process is one of the factors that impacts LWR. Enhancing track processes in EUV lithography is thus critical to controlling LWR. This paper describes an approach to mitigating LWR based on optimizing track-based and etch-based processes. It also presents the results of our newly developed track-based smoothing process as well as the results of combining several track-based techniques. The latest LWR performance from using track-based techniques, optimized track processes, and etch-based techniques will be highlighted.

Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications

Multiple patterning integrations for sub 193nm lithographic resolution are becoming increasingly creative in pursuit of cost reduction and achieving desired critical dimension. Implementing these schemes into production can be a challenge. Aimed at reducing cost associated with multiple patterning for the 10nm node and beyond, we will present a self-aligned quadruple patterning strategy which uses 193nm immersion lithography resist pattern as a first mandrel and a spacer on spacer integration to enable a final pitch of 30nm. This option could be implemented for front end or back end critical layers such as Fin and Mx. Investigation of combinations of low temperature ALD films such as TiO, Al2O3 and SiO2 will be reviewed to determine the best candidates to meet the required selectivities, LER/LWR and CDs.

Resist process applications to improve EUV patterning

Roughness control is a key technical issue in extreme ultraviolet (EUV) lithography. It applies to both line and space (L/S) and contact hole (C/H) structures. Recently, SEMATECH and Tokyo Electron Limited (TEL) developed several track-based techniques, including developer optimization, FIRM™ (Finishing up by Improved Rinse Material), and smoothing to reduce structural roughness. The combination of these techniques improved line width roughness (LWR) about 25% from the 2011 baseline of 32 nm L/S. C/H structures were also tested with the combination process. This paper describes our latest L/S and C/H roughness performance post-lithography and postetch. A feasibility study of negative tone develop (NTD) resists for EUV is also included.

DSA patterning options for FinFET formation at 7nm node

Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.

DSA patterning options for logics and memory applications

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme

Patterning the desired narrow pitch at 10nm technology node and beyond, necessitates employment of either extreme ultra violet (EUV) lithography or multi-patterning solutions based on 193nm-immersion lithography. With enormous challenges being faced in getting EUV lithography ready for production, multi-patterning solutions that leverage the already installed base of 193nm-immersion-lithography are poised to become the industry norm for 10 and 7nm technology nodes. For patterning sub-40nm pitch line/space features, self-aligned quadruple patterning (SAQP) with resist pattern as the first mandrel shows significant cost as well as design benefit, as compared to EUV lithography or other multi-patterning techniques. One of the most critical steps in this patterning scheme is the resist mandrel definition step which involves trimming / reformation of resist profile via plasma etch for achieving appropriate pitch after the final pattern. Being the first mandrel, the requirements for the Line Edge Roughness (LER) / Line Width Roughness (LWR); critical dimension uniformity (CDU); and profile in 3-dimensions for the resist trim / reformation etch is extremely aggressive. In this paper we highlight the unique challenges associated in developing resist trim / reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.

Fin formation using graphoepitaxy DSA for FinFET device fabrication

A 27nm-pitch Graphoepitaxy directed self-assembly (DSA) process targeting fin formation for FinFET device fabrication is studied in a 300mm pilot line environment. The re-designed guiding pattern of graphoepitaxy DSA process determines not only the fine DSA structures but also the fin customization in parallel direction. Consequently, the critical issue of placement error is now resolved with the potential of reduction in lithography steps. However, challenges in subsequent pattern transfer are observed due to insufficient etch budget. The cause of the issues and process optimization are illustrated. Finally, silicon fins with 100nm depth in substrate with pre-determined customization is demonstrated.

Optimization of low-diffusion EUV resist for linewidth roughness and pattern collapse on various substrates

This paper will report on our development of low diffusion EUV resists based on polymer-bound PAG technology. With our low diffusion resist, a wide process window for 30-nm hp of 280nm DOF over a 10% exposure range is achieved on a prototype ADT fullfield scanner. Linewidth roughness of 3.1nm is also achieved. Excellent resist profiles can be achieved on organic ULs or Si hardmask materials. This resist also shows only 1.1 nm carbon growth on witness plate mirrors for cleanables, and no reflectivity loss after mirror cleaning. These results clearly pass for use on all NXE exposure tools. We also have shown good pattern transfer for a Si HM stack using this resist. Finally, we report 17-nm hp resolution at a dose of 14.5mj for a higher absorption resist.