David Iezzi

Power efficient charge pump in deep submicron standard CMOS technology

A power efficient charge pump is proposed. The use of low voltage transistors and of a simple 2-phase clocking scheme allows the use of higher frequencies compared to conventional solutions, thus obtaining high current, high efficiency and small area. Measurements show good results for frequencies around 100MHz. Two testpatterns have been fabricated, one with three stages and one with five stages, in a 1.8V 0.18micro;m standard CMOS digital process (6 metals) with triple well. High voltage capacitors have been implemented using metal to metal parasitic capacitance.

A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory

A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18um, 2PL-6ML CMOS Flash technology, chip area is 70mm2.

A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

A 1 GOPS dynamically reconfigurable processing unit with embedded flash memory and SRAM-based FPGA for image/voice processing/recognition applications is described. Code, data and FPGA bitstreams are stored in the embedded flash memory and are independently accessible through 3 content-specific, 64 b I/O ports with a peak read rate of 1.2 GB/s. The system is implemented in a 0.18 /spl mu/m 2P 6M CMOS flash technology with a chip area of 70 mm/sup 2/.

An application specific embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations

A 8 Mb application-specific embeddable flash memory is presented. It features 3 content-specific I/O ports, delivers a peak read throughput of 1.2 GB/S, and, combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18 /spl mu/m flash embedded technology with 1.8 V power supply, 2 poly, 6 metal and memory cell size of 0.35 /spl mu/m/sup 2/.