Giovanni Guaitini

1 M-cell 6b/cell analog flash memory for digital storage

This standard flash-EEPROM contains 1 M cells with multi-level programming of up to 64 digital levels per cell, providing a prototype of a 6 Mb memory with 257 Mb/cm/sup 2/ array density.

A current driven, programmable gain differential pair using MOS translinear circuits

In this paper a novel current-mode CMOS differential pair which uses the translinear principle is suggested. The shape of the sigmoidal input-output function can be adjusted through a tuning current over a wide operating range. A design example of the circuit applied to the implementation of an analog VLSI neural system is presented.

A CMOS analog neuro-chip with stochastic learning and multilevel weight storage

The chip, fabricated in a 1.0 /spl mu/m CMOS technology, has a 2-dimension input vector, 16 neurons, 112 weights, each one with a multilevel storage circuit, 28 internal uncorrelated noise sources, a random weight change learning algorithm implemented on-chip and weight access capability.

An Analog CMOS Neural Network with On-Chip Learning and Multilevel Weight Storage

An analog neural network with four neurons and 16 synapses, fabricated in a 1.2 μm n-well single-polysilicon, double-metal process, is presented. The circuit solutions adopted, for on-chip learning and weight storage, particularly simple and silicon area-efficient, are capable of solving the main problems to the implementation of analog neural networks.