David Jerome Johnson

Bi-directional linear feedback shift register

Associative cache memory with improved hit time

Speculative pre-flush of data in an out-of-order execution processor system

Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor

Preemptive eviction of stale entries is a computer cache by use of age-bits

Identification of stale entries in a computer cache

Adaptive hysteresis receiver for a high speed digital signal

Cache memory entry eviction method for multiprocessor system, involves evicting entry if age bit provided for each line or index, remains at logical ONE after preset time, after being set to logical one

Präemptive Räumung veralteter Einträge in einem Computer-Cache durch die Verwendung von Alters-Bits

pre-extraction system of data speculative execution in a processor system not orderly instruction