Jonathan P. Lotz

A quad-issue out-of-order RISC CPU

A 64 b 4-way superscalar PA-RISC microprocessor system operating from 150-250 MHz combines full out-of-order execution with low-cycle time, to produce >360 specint and >550 specfp. Specialized latching and clock circuits and extensive use of dynamic logic enable high frequency operation. 3.8 M logic transistors are integrated on a 17.68/spl times/19.1 mm/sup 2/ die in 3.3 V 0.5 /spl mu/m CMOS.

A CMOS RISC CPU designed for sustained high performance on large applications

A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAMs. Key performance features include a 3.5-ns 32-b adder, low skew on-chip clock buffers, and cycling large off-chip caches at the operating frequency. The chip has been fabricated using a 1.0- mu m CMOS process that utilizes three-level metal and 480000 transistors on a 14*14-mm die. >

A 90 MHz CMOS RISC CPU designed for sustained performance

A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard synchronous static random-access memories (SRAMs). The speeds obtained are comparable to those of many emitter-coupled logic (ECL) implementations. The CPU chip includes the following hardware: integer fetch and execute unit, on-chip split I/D TLBs (translation lookaside buffers) with two-way 64 entries each, control for second-level off-chip TLBs, control for off-chip two-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, inference for performance analysis and tuning, and a tightly coupled coprocessor interface.<<ETX>>