Gregg B. Lesartre

System and method for on-chip debug support and performance monitoring in a microprocessor

Method for processing information in a microprocessor to facilitate debug and performance monitoring

Circuitry for providing external access to signals that are internal to an integrated circuit chip package

Cache line replacement using cache status to bias way selection

Store-to-load hazard resolution system and method for a processor that executes instructions out of order

Flexible circuitry and method for detecting signal patterns on a bus

Operand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data words

Response Control for Memory Modules That Include or Interface With Non-Compliant Memory Technologies

Apparatus and method for reading and writing remote registers on an integrated circuit chip using a minimum of interconnects

Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache