David Leroy Guertin

VLSI performance compensation for off-chip drivers and clock generation

A major problem in VLSI system design is controlling off-chip driver characteristics and skew in clock generation as process parameters, temperature, and supply voltage vary. A control circuit methodology has been developed that senses the relative performance of a CMOS chip and transmits a digitally encoded state to off-chip driver and clock generation circuits to control their operating characteristics

Design and packaging challenges for on-board cache subsystems using source synchronous 400 Mb/s interfaces

This paper describes circuit and packaging design challenges encountered while attempting to optimize the source synchronous timing equations for the system level interconnects using a 200 MHz double data rate (DDR) level 3 (L3) cache subsystem. Various solutions to these challenges are presented. The delay skew budget and noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated delay skew control techniques.