Douglas W. Stout

Managing power and performance for system-on-chip designs using Voltage Islands

This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

VLSI performance compensation for off-chip drivers and clock generation

A major problem in VLSI system design is controlling off-chip driver characteristics and skew in clock generation as process parameters, temperature, and supply voltage vary. A control circuit methodology has been developed that senses the relative performance of a CMOS chip and transmits a digitally encoded state to off-chip driver and clock generation circuits to control their operating characteristics

I/O impedance matching algorithm for high-performance ASICs

This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given.

Technology-migratable ASIC library design

A library strategy has been developed to enable IBM Microelectronics ASIC development to keep pace with rapid technology enhancements and to offer leading-edge performance to ASIC customers. Library elements are designed using migratable design rules to allow designs to be reused in future advanced technologies; and library contents, design methodology, test methodology, and packaging offerings for the ASICs also are consistent between current and future technologies. The benefit to the ASIC customer is an ASIC with a rich library of logic functions, arrays, and I/Os for todays designs, and with a ready migration path into future designs.

The first copper ASICs: A 12M-gate technology

This paper describes the first CMOS ASIC logic family built with copper metallurgy. Chips with up to 12-million equivalent gates can be designed in the 0.16 /spl mu/m process. The technology, product characteristics, CAD system and first customer chips are discussed.

Gate-array library design using local interconnect

An ASIC gate-array library has been created in 0.4 /spl mu/m CMOS technology using a local interconnect level. The gate-array cells in this library are denser than their counterparts in a library without local interconnect. The comparison of two benchmarks, including a 520K-gate ASIC routed with both libraries, further shows that the local interconnect allows higher density of ASIC designs due to more efficient use of the global inter-connect layers.