David Milford

Road edge tracking for robot road following: a real-time implementation

Abstract The problem of visually navigating a robot along a road is approached by means of creating and updating a simple representation of the road from a sequence of images. The representation chosen is a 4-parameter model that describes the width, direction and simple curvature of the road in a vehicle centred (X, Y, Z) world coordinate system. The model is created by tracking along major edge features in an image and applying constraints to select road edge candidates. Updating consists of tracking a set of measured edge points from frame to frame (assuming that vehicle motion is known), and using a weighted least squares process to find the four parameters of the road model. A number of constraint and filtering processes representing knowledge of how a vehicle moves on a road have been applied. The algorithm has been developed to run at near real-time video rates.

A new modulo 2/sup a/+1 multiplier

This paper presents the design of a new modulo 2/sup a/ + 1 multiplier. It makes use of the redundancy in the binary representation of numbers in the finite integer ring R(2/sup 1/+1), though, unlike in some other designs, code translations are not involved. The use of the periodic properties of powers of two taken modulo 2/sup a/+1 simplifies the result correction process and permits a highly regular circuit structure which is suitable for VLSI implementation. Since the multiplier is almost exclusively composed of full and half adders, it can easily be pipelined with throughput reaching hundreds of megahertz. Such performance should make the implementation very attractive in many DSP applications.<<ETX>>

Road Edge Tracking for Robot Road Following.

The problem of navigating a robot along a road is approached by means of creating and updating a simple representation of the road from a sequence of images. The representation chosen is a 4-parameter model that describes the width, direction and simple curvature of the road in a vehicle centred (X,Y,Z) world coordinate system. The model is created from tracking along major edge features in an image and applying constraints to select road edge candidates. Updating consists of tracking a set of measured edge points from frame to frame (assuming that vehicle motion is known) and using a weighted least squares process to find the 4 parameters of the road model. A number of constraint and filtering processes representing knowledge of how a vehicle moves on a road have been applied.

Real-time vision guided navigation

Abstract This paper presents an overview of a three-year investigation into vision-guided road vehicle control conducted by a team at the University of Bristol. The goal has been to develop a parallel computer architecture, based on the Inmos transputer, which is capable of real-time analysis of video images obtained from a camera mounted on the front of a vehicle. Much of our algorithm development has been based on analysis of pre-recorded videos of typical road scenes. However, one version of our system is battery powered and small enough to reside entirely on a small electric vehicle that we use as a demonstrator. The algorithms we are investigating are parallelised to a sufficient degree to allow them to operate at near frame rates (10–20 frames per s). We have adopted two principal approaches: road edge detection, and surface segmentation. Our vehicle is presently capable of successfully negotiating several hundred yards without mishap on small roads and paths in the University grounds. Recent work involves the design of a more-modular parallel vision system together with a somewhat larger and faster demonstration vehicle. The principle behind the new system is that each module, including those governing the vehicle, should be controlled by a single transputer. Thus, the top level of the configuration is simply a network of transputers connected by links. Progress on this system is reported.

A new approach to fixed-coefficient inner product computation over finite rings

Inherently parallel arithmetic based on the residue number system (RNS) lends itself very well to implementation of high-speed digital signal processing (DSP) hardware. In most cases, DSP computations can be decomposed to the inner product form Y=/spl Sigma//sub i=0//sup N-1/C/sub i/X/sub i/. Therefore, implementation of the inner product computation over finite rings is of paramount importance for RNS-based DSP hardware. Recently, periodic properties of residues of powers of 2 have been found useful in designing residue arithmetic circuits. This paper presents a deeper insight to the periodicity concepts by applying abstract algebra and number theory methods. Advantage is taken of the fact that the set Z/sub m//sup +/={1, 2, ..., m-1} splits completely, with respect to some g/spl isin/Z/sub m//sup +/, into sets which are closed under multiplication by g modulo m. Properties of such a decomposition of Z/sub m//sup +/ are investigated and the theory is applied to develop new fixed-coefficient inner product circuits for finite-ring arithmetic. The new designs are almost exclusively composed of full adders and they can easily be pipelined to achieve very high throughput. A VLSI implementation study of the new inner product circuits is presented. It shows that, compared with the best method known to date, both smaller area requirements and higher throughput are achieved.

Road Edge Extraction Using a Plan-View Image Transformation.

A new technique to extract road edges in the roadfollowing algorithm for autonomous road vehicle navigation is described. It is based on finding road edges on a subsampled plan-view of a portion of the road ahead of the vehicle. The method is illustrated in the real-time identification of road edges using a fast vertical edge detector and link operator applied to the transformed plan view. Location of both road edges at 20 frames per second is demonstrated.

Using SILVAR-LOSCO for logic cell array design

Instead of gate arrays, the logic cell array (LCA) has been used as the implementation medium in an undergraduate design exercise. Software has been written to link the SL-2000 database to the LCA layout and routing system (XACT). The result has been improved student motivation and a higher proportion of completed designs.

CAD tools for semicustom IC design

Abstract Recent papers in this journal1,2 have provided an overview of semicustom design and descriptions of the most widely used semicustom technologies: gate arrays and cell-based ICs. This paper presents a survey of the various CAD tools which enable an electronic design engineer to use semicustom technology. It will be shown that the necessity for any specialized knowledge of silicon-level design is largely removed.

Computation of fixed-coefficient inner products over finite rings with the use of pass-transistor networks

This paper presents new designs of fixed-coefficient inner product circuits for finite-ring arithmetic. These circuits are crucial for residue number system (RNS) based digital signal processing (DSP) systems, where computations can often be decomposed to the inner product form. The approach proposed is based on pass-transistor networks and one-hot data representation. Hardware complexity of the new circuits has been analyzed showing that substantial hardware savings can be achieved, compared to implementations based on the bit-sliced inner product step processor (BIPSP/sub m/). A low-cost double-edge-triggered data register has been developed for the new inner product circuits which can also be used in various other pipelined designs.

Design of synchronous parallel controllers for low-power applications

Transition signalling is a convention whereby any signal transition has the same meaning and is interpreted as an event. Such a conceptual framework is particularly well suited to asynchronous circuit design, where it has been successfully employed. This paper investigates how transition signalling can be used in the design of synchronous parallel controllers to reduce power consumption. Experimental results of controller implementation are encouraging, especially for highly parallel systems, where significant power savings can be achieved. Double-edge-triggered (DET) flip-flops, which provide a power-efficient solution to the realization of data registers, can easily be interfaced with synchronous controllers based on transition signalling. This makes the new approach a very attractive option for low-power system design.