Erik L. Dagless

Road edge tracking for robot road following: a real-time implementation

Abstract The problem of visually navigating a robot along a road is approached by means of creating and updating a simple representation of the road from a sequence of images. The representation chosen is a 4-parameter model that describes the width, direction and simple curvature of the road in a vehicle centred (X, Y, Z) world coordinate system. The model is created by tracking along major edge features in an image and applying constraints to select road edge candidates. Updating consists of tracking a set of measured edge points from frame to frame (assuming that vehicle motion is known), and using a weighted least squares process to find the four parameters of the road model. A number of constraint and filtering processes representing knowledge of how a vehicle moves on a road have been applied. The algorithm has been developed to run at near real-time video rates.

Road Edge Tracking for Robot Road Following.

The problem of navigating a robot along a road is approached by means of creating and updating a simple representation of the road from a sequence of images. The representation chosen is a 4-parameter model that describes the width, direction and simple curvature of the road in a vehicle centred (X,Y,Z) world coordinate system. The model is created from tracking along major edge features in an image and applying constraints to select road edge candidates. Updating consists of tracking a set of measured edge points from frame to frame (assuming that vehicle motion is known) and using a weighted least squares process to find the 4 parameters of the road model. A number of constraint and filtering processes representing knowledge of how a vehicle moves on a road have been applied.

Real-time vision guided navigation

Abstract This paper presents an overview of a three-year investigation into vision-guided road vehicle control conducted by a team at the University of Bristol. The goal has been to develop a parallel computer architecture, based on the Inmos transputer, which is capable of real-time analysis of video images obtained from a camera mounted on the front of a vehicle. Much of our algorithm development has been based on analysis of pre-recorded videos of typical road scenes. However, one version of our system is battery powered and small enough to reside entirely on a small electric vehicle that we use as a demonstrator. The algorithms we are investigating are parallelised to a sufficient degree to allow them to operate at near frame rates (10–20 frames per s). We have adopted two principal approaches: road edge detection, and surface segmentation. Our vehicle is presently capable of successfully negotiating several hundred yards without mishap on small roads and paths in the University grounds. Recent work involves the design of a more-modular parallel vision system together with a somewhat larger and faster demonstration vehicle. The principle behind the new system is that each module, including those governing the vehicle, should be controlled by a single transputer. Thus, the top level of the configuration is simply a network of transputers connected by links. Progress on this system is reported.

An associative processor array for image processing

Abstract This paper describes work carried out on associative processor arrays for image processing. The architecture of a new VLSI associative processor, called GLiTCH, is defined and compared with similar image processing arrays. Simulation results are presented for GLiTCH systems performing a range of image processing tasks.

A new approach to fixed-coefficient inner product computation over finite rings

Inherently parallel arithmetic based on the residue number system (RNS) lends itself very well to implementation of high-speed digital signal processing (DSP) hardware. In most cases, DSP computations can be decomposed to the inner product form Y=/spl Sigma//sub i=0//sup N-1/C/sub i/X/sub i/. Therefore, implementation of the inner product computation over finite rings is of paramount importance for RNS-based DSP hardware. Recently, periodic properties of residues of powers of 2 have been found useful in designing residue arithmetic circuits. This paper presents a deeper insight to the periodicity concepts by applying abstract algebra and number theory methods. Advantage is taken of the fact that the set Z/sub m//sup +/={1, 2, ..., m-1} splits completely, with respect to some g/spl isin/Z/sub m//sup +/, into sets which are closed under multiplication by g modulo m. Properties of such a decomposition of Z/sub m//sup +/ are investigated and the theory is applied to develop new fixed-coefficient inner product circuits for finite-ring arithmetic. The new designs are almost exclusively composed of full adders and they can easily be pipelined to achieve very high throughput. A VLSI implementation study of the new inner product circuits is presented. It shows that, compared with the best method known to date, both smaller area requirements and higher throughput are achieved.

DART: delay and routability driven technology mapping for LUT based FPGAs

A two-phased approach for routability directed delay-optimal mapping of LUT based FPGAs is presented based on the results of stochastic routability analysis. First, delay-optimal mapping is performed which simultaneously minimizes area and delay. Then, the mapped circuits are restructured to alleviate the potential routing congestions. Experimental results indicate that the first phase creates designs which require 17% fewer levels and 40% fewer LUTs than MIS-pga (delay), 11% fewer levels and 37% fewer LUTs than FlowMap-r, and 5% fewer levels and 39% fewer LUTs than TechMap-D. The success of the second phase is confirmed by running a vendors layout tool APR. It is observed that they are more routable and have less final delays than those produced by other mappers if they are placed and routed.

Road Edge Extraction Using a Plan-View Image Transformation.

A new technique to extract road edges in the roadfollowing algorithm for autonomous road vehicle navigation is described. It is based on finding road edges on a subsampled plan-view of a portion of the road ahead of the vehicle. The method is illustrated in the real-time identification of road edges using a fast vertical edge detector and link operator applied to the transformed plan view. Location of both road edges at 20 frames per second is demonstrated.

Real-Time Number Plate Reading

Abstract Vehicle number plate recognition systems are expected to have numerous applications in traffic surveying and monitoring, e.g. finding stolen cars and controlling access to car parks. In this paper algorithmic improvements to a previous version of a number plate reading system are described. The work builds on the experience gained by the Computer Vision Group at the University of Bristol. This paper addresses the problem of locating the number plate area in the image and proposes a new line based method for number plate location, which is suitable for realtime number plate recognition.

Autonomous road vehicle navigation

Abstract This paper describes a new modular hardware design for an autonomous land vehicle, together with techniques for navigation and obstacle avoidance. A “bootstrap” algorithm is described which aligns the vehicle from an arbitrary starting point using the roads vanishing point. An algorithm to perform navigation along a structured road is then described. This is achieved by modelling the white lane-boundary marking using six parameters which are updated iteratively from frame to frame using a non-linear least-squares techniques. The obstacle-detection method is based on frame differencing. Using data from the vehicle odometry sensors, a motion-corrected version of the difference between frames is produced, in which objects projecting up from the ground plane are easily identified.

An associative processing module for a heterogeneous vision architecture

The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes images and extract features, and a MIMD network of transputers processes extracted objects in parallel. The arrays VLSI implementation, the processing modes available due to the use of content-addressable memory, and the means of achieving efficient 2-D interprocessor communication in the linear array are described. An application as a vehicle number plate recognition system is presented.<<ETX>>