David Overhauser

Clock skew verification in the presence of IR-drop in the power distribution network

Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical. In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

Full-chip verification methods for DSM power distribution systems

Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed power distribution systems. This paper describes an efficient approach for the verification of power distribution at the full-chip transistor level based on a combination of hierarchical static and dynamic techniques. Application of the methodology on practical design examples is provided. We also demonstrate the necessity of analysis at the full-chip transistor level to verify the complex interactions between different design blocks based on static and dynamic effects.

Clock verification in the presence of IR-drop in the power distribution network

Clock nets are the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of the clock signal directly impacts the performance of a VLSI chip. Clock verification requires high accuracy and is typically performed using circuit simulators. In high-performance deep-submicron digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher load on the power distribution network with the potential of substantial IR-drop. However, as IR-drop is a full-chip phenomenon, circuit simulation is extremely time consuming. In this paper, we present a loosely coupled iterative technique for clock verification in the presence of full-chip dynamic IR-drop. The degradation in the clock signal due to dynamic IR-drop is demonstrated on a small example as well as upon a large chip. In addition, we also discuss risks associated with assuming a static IR-drop budget upon clock propagation.

Full-chip verification of UDSM designs

The article describes the problems encountered in typical ultra-deep submicron (UDSM) designs, and the full-chip interconnect verification methodologies needed to successfully identify these problems before tape-out. We first illustrate that UDSM verification must go well beyond simple geometric and circuit comparison checks to address increasingly important issues such as timing, power integrity, signal integrity, and reliability. The key issues of IR drops in the power grid, electromigration in power and signal lines, clock skew, signal coupling and its effect on timing and noise are described. We present real world examples of such problems and how to find these problems using full chip verification.

Methods to improve digital MOS macromodel accuracy

This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances, and the body effect. Adequate solutions to address these sources of delay errors, which may total 100% or more, have not been previously provided. The significant improvement in simulation accuracy using these proposed techniques is shown. The timing macromodel used to implement these techniques is up to several hundred times faster than SPICE2 and up to several times faster than existing nonlinear macromodels. The accuracy of this macromodel over a wide range of operating conditions is demonstrated. The macromodel and reduction techniques can be used to minimize VLSI simulation time, provide fast feedback in circuit optimization, and generate accurate data for higher-level macromodels. The proposed reduction techniques apply to linear and nonlinear macromodels. >

Performance estimation of complex MOS gates

In this paper, a new efficient two-step reduction technique is proposed to estimate the performance of complex gates. A complex gate is first mapped to an equivalent NAND gate form and then the NAND gate is mapped to an inverter macromodel. Accurate reduction techniques for series-connected transistors precisely model effective transconductance, the channel length modulation effect, input terminal position dependence, parasitic capacitances, and the body effect. Adequate solutions to address these sources of delay errors, which may total 100% or more, have not been previously provided. These reduction techniques are not tied to a single macromodel, but generally are applicable to existing linear and nonlinear macromodels. Experiments with a wide range of input transitions and output loadings for various gates show nearly identical results between SPICE2 and the proposed techniques. The proposed macromodeling techniques are up to several hundred times faster than SPICE2 and up to several times faster than existing nonlinear macromodels for individual gates.

Switch-Level Timing Simulation of MOS VLSI Circuits

1. Introduction.- 2. Overview of Simulation Techniques.- 2.1 Analog vs Digital Simulation.- 2.2 Gate-Level Simulation.- 2.3 Switch-Level Logic Simulation.- 2.4 Mixed-Mode or Hybrid Simulation.- 2.5 Switch-Level Timing Simulation.- 3. Mos Network Partitioning and Ordering.- 3.1 MOS Network Components and Models.- 3.2 Partitioning the MOS Network into Blocks.- 3.2.1 Review of Graph Theory.- 3.2.2 Blocks of an MOS Network.- 3.2.3 Partitioning Algorithm and Its Complexity.- 3.2.4 A CMOS Example.- 3.3* Partitioning into Driver and Pass Transistors.- 3.3.1 Motivation.- 3.3.2 Formal Definitions.- 3.3.3 Partitioning Algorithm.- 3.3.4 An NMOS Example.- 3.3.5 Modifications for CMOS Circuits.- 3.4 Ordering of Partitioned Blocks.- 3.4.1 Directed Graphs.- 3.4.2 Presence of Feedback and Its Detection.- 3.4.3 An Example to Illustrate Ordering.- 3.5 Conclusions.- 4. Switch-Level Timing Simulation.- 4.1 Overview.- 4.2 Waveform Representation.- 4.3 Simulation Algorithm.- 4.4 Deriving Inverter Voltage Equations.- 4.4.1 Equations for Switching Inputs.- 4.4.2 Equations for Fixed Inputs.- 4.4.3 Using the Equations.- 4.5 Determining the dc Output Voltage.- 4.6 Mapping Complex Blocks to Primitives.- 4.6.1 Transistor Reduction Basis.- 4.6.2 Subcircuit Reduction Algorithm.- 4.7 Parasitics.- 4.8 Sample Subcircuit Processing.- 4.8.1 Simple CMOS Inverter.- 4.8.2 CMOS NAND Gate.- 4.8.3 NMOS Inverter Driving a Pass Transistor.- 5. Simulating Strongly Connected Components.- 5.1 Waveform Relaxation vs Time-point Relaxation.- 5.2 Dynamic Windowing.- 6. Performance of Idsim2.- References.- About The Authors.

Full-chip reliability analysis

Abstract Reliability analysis has not been promoted to the realm of full-chip because techniques to extract, manage, and process full-chip power grid and signal data have not been previously available. This paper introduces techniques that have been developed to permit both full-chip power grid and signal net electromigration and Joule heating analysis. Results of this analysis provide feedback to the designer to permit easy design modification to provide superior “designed-in” long-tern reliability.

Digital Timing Macromodeling for VLSI Design Verification

List of Figures. List of Tables. Preface. 1. Introduction. 2. Survey of Simulation and Macromodeling Techniques. 3. A Nonlinear Macromodel. 4. Reduction Techniques for Complex Gates. 5. Accounting for RC- Interconnects. 6. Transmission Gate Modeling. 7. Conclusions. A. The SPICE Level 2 Model. B. Nonlinear Macromodel Output Response Derivations. C. The Derivation of M = 0.5 Heuristic in Reduction Techniques. D. Delay Errors for Various AOI Gates. References. Index.

Power distribution in high-performance design

Power distribution design in high-performance chips is a task that is not eased through the application of power reduction techniques. Although the average power of a high-performance design can be reduced, the peak to average power current ratio of blocks increases as a result, aggravating the challenges faced prior to average power reduction. This paper discusses the power distribution design challenge: to reliably deliver a predictable voltage to all transistors under all operating conditions. Steps in power estimation, approaches to power distribution implementation, and verification of power distribution are reviewed. The myths versus reality of power distribution design in high-performance chips are provided.