Jeong-Taek Kong

Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

PowerV i P: Soc power estimation framework at transaction level

In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design

An MTCMOS design methodology and its application to mobile computing

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsungs 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling

In this paper, the influence of floating dummy metal-fills on interconnect parasitic is analyzed with the variations of possible factors which can affect the capacitance. Recently proposed chip-level metal-fill modeling, replacing metal-fill layer with effective high-k dielectric, has been reviewed in detail. Using a systematized modeling flow, the property of the effective permittivity in the modeled geometry is examined. Validation with the realistic 3D structures clearly demonstrates the importance and correctness of the geometry modeling.

An exhaustive method for characterizing the interconnect capacitance considering the floating dummy-fills by employing an efficient field solving algorithm

This paper presents an exhaustive method to characterize the interconnect capacitances while taking the floating dummy-fills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is implemented into the 3D finite-difference solver and its computational efficiency is compared with the industry-standard RAPHAEL. Furthermore, the overall flow for extracting the parasitic capacitance considering the dummy-fills at the full-chip level is discussed and the underlying assumption is examined.

Analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip RC extraction

Studies the effects of dummy-fills on the interconnect capacitance and the global planarity of chips in order to provide the design guideline of the dummy-fills. A simple but accurate full-chip RC extraction methodology taking the floating dummy-fills into account is proposed and applied to the analysis of changes in capacitance and signal delay of the global interconnects, for the first time. The results for 0.18 /spl mu/m designs clearly demonstrate the importance of considering floating dummy-fills in the interconnect modeling and the full-chip RC extraction.

Reliability Issues and Models of sub-90nm NAND Flash Memory Cells

The reliability issues, including 100k cycles endurance and 2 hours high temperature storage (HTS: 150degC, 200degC and 250degC) of sub-90nm NAND flash cells, are studied. Furthermore, the trap generation models in endurance and interface trap recovery model in HTS are proposed. Endurance characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count (DeltaNit, DeltaNot infin cycleuarrm). The exponent of interface trap generation both program and erase are 0.62; while in bulk trap generation, the exponent for the cycle count is 0.30, which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide degradation. The HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND flash memory, while stress induced leakage current (SILC) is almost negligible. Thus, based on the reaction-diffusion (R-D) model and Arrhenius approximation, the simplified interface recovery model in HTS is proposed as: dNit/Nit = -k0 middot exp(-Ea/kBT) middot dt

CAD for nanometer silicon design challenges and success

As silicon CMOS technology is scaled into the nanometer regime, the paradigm shift of computer-aided design (CAD) technology is indispensable to cope with two major challenges (i.e., the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology). System-level design and verification methodologies manage the functional complexity, and manufacturing-aware design techniques control the nanoscale physical effects. In this highlight paper, most nanometer design issues are described and the issues related to the higher level of abstraction are summarized. Process variability can be controlled by statistical design, resolution enhancement, planarity control, and other manufacturing-aware design techniques. Continuously growing problems such as leakage power, signal integrity, and reliability are also discussed. Finally, technology CAD for future nanometer devices is presented. For successful nanometer silicon design, closer cooperation among the design, process technology, mask, and CAD communities are essential.

Automatic gate CD control for a full-chip-scale SRAM device

As the minimum feature size in VLSI circuits is reduced less than the wavelength of the exposure light, resolution enhancement technologies (RETs) have been developed. Optical proximity correction (OPC), which is one of RETs, can correct the difference in line width between isolate lines and lines in a dense array. Among the factors of CD variation (i.e., the optical proximity effect, numerical aperture, partial coherence, swing effect, and CD error on a mask), we have found that the optical proximity effect causes a severe isolate-dense bias larger than 35 nm. The optical proximity effect was corrected using an automatic tool based on an optical behavioral model. To determine the optimum threshold intensity, test patterns with the various threshold values were produced and measured using SEM. From this experiment, a proper threshold has been chosen and applied to a full chip pattern except the cell area in the gate layer of an SRAM device, which is optimized by photo engineers experience. Furthermore, a model recipe correcting only the line width was set up to prevent the increase of the e-beam data size in two dimensional correction. Up to 40% reduction of CD variation can be expected, considering that more than 50% of gate layer patterns have the error distribution of -10 nm to 10 nm after OPC.

Programming characteristics of phase change random access memory using phase change simulations

We present a new simulation methodology for analyzing programming characteristics of a chalcogenide based phase-change device, phase change random access memory (PRAM), which is a next-generation non-volatile memory. Using the new simulation methodology, we analyze the initialization of chalcogenide material (ICM) of the mechanism and propose the next generation PRAM scheme. From the results of the phase change simulation, the process conditions for ICM for stable operation are presented. Also, the self-heating confined structure to overcome the inherent limitation of high operation power is proposed that resolves the operating power limitation associated with PRAM development.