David P. Brunco

High-Performance Deep Submicron Ge pMOSFETs With Halo Implants

Ge pMOSFETs with HfO2 gate dielectric and gate lengths down to 125 nm are fabricated in a Si-like process. Long-channel hole mobilities exceed the universal curve for Si by more than 2.5 times for vertical effective fields as large as 1 MV/cm. The mobility enhancement is found to be relevant at submicron gate lengths, and a drive current of 1034 muA/mum is achieved for L=125 nm at VG-VT=VD=-1.5 V. The introduction of halo implants allows significantly improved control of short-channel effects, with approximately three orders of magnitude reduction in source junction off-current. VT rolloff and drain-induced barrier lowering are reduced from 207 mV and 230 mV/V to 36 mV and 54 mV/V, respectively, for the highest n-well dose investigated. Four key logic benchmarking metrics are used to demonstrate that Ge is able to outperform Si down to the shortest investigated gate length, with an almost twofold improvement in intrinsic gate delay. ION=722 muA/mum is demonstrated for IOFF=11 nA/mum at a power supply voltage of -1.5 V, when evaluating from the source.

Complete experimental test of kinetic models for rapid alloy solidification

The interface response functions for rapid solidification of a non-dilute binary alloy were measured in the regime of partial solute trapping, where substantial discrepancies exist among predictions for the interfacial undercooling in various models. We used pulsed laser melting of Si-As on insulating substrates to enforce planar solidification spanning the velocity range 0.2-2 m/s. Nanosecond-resolution electrical measurements of the time-dependent melt depth and of the electrical resistivity of a buried Pt thin film thermometer permitted us to determine the solidification velocity and the temperature of the crystal/melt interface. With composition-depth profile measurements we also determined the nonequilibrium partition coefficient. The measured velocity-dependence of the interface temperature and partition coefficient are quan- titatively consistent with the continuous growth model without solute drag of M. J. Aziz and T. Kaplan (Acta Metall. 36, 1335 (1988)) and are qualitatively and quantitatively inconsistent with all models exhibiting a significant solute drag effect. Elements of a potential explanation are proposed using the solute drag model of M. Hillert and B. Sundman (Acta Metall. 24, 731 (1976)) to investigate the origin of the solute drag effect in terms of irreversible processes occurring within a diffuse interface.

Germanium partitioning in silicon during rapid solidification

Pulsed laser melting experiments were performed on GexSi1−x alloys (x≤0.10) with regrowth velocities ranging from 0.25 to 3.9 m/s. Analysis of post‐solidification Ge concentration profiles, along with time‐resolved melt depth measurements, allowed determination of the liquid‐phase diffusivity Dl for Ge in Si and the dependence of the Ge partition coefficient k on interface velocity v. A Dl of 2.5×10−4 cm2/s was measured. The k vs v data were analyzed using various models for partitioning, including both the dilute and nondilute Continuous Growth Models (CGM). Extrapolating to zero velocity using the partitioning models, an equilibrium partition coefficient of approximately 0.45 was obtained. Best fitting of partitioning data to the nondilute CGM yields a diffusive speed of 2.5 m/s. These measurements quantify previous indications of partitioning observed in other studies of pulsed laser processed GexSi1−x alloys.

Electron energy band alignment at interfaces of (100)Ge with rare-earth oxide insulators

Energy diagrams of interfaces between (100)Ge and several rare-earth oxide insulators deposited from a molecular beam are determined using a combination of internal photoemission and photoconductivity measurements. For the wide band gap (5.9eV) oxides Gd2O3 and LaHfOx, the band alignment at the interface is found to be close to that of HfO2 and is characterized by conduction/valence band offsets of ∼2∕∼3eV. In contrast, CeO2 which has a much narrower band gap (3.3eV) does not provide a band alignment diagram corresponding to sufficient insulation.

Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.

Observation and Suppression of Nickel Germanide Overgrowth on Germanium Substrates with Patterned SiO2 Structures

We have investigated the reactions of thin Ni films on Ge-on-Si substrates with patterned SiO 2 structures. For rapid thermal anneals (RTAs) hotter than ∼300°C, an undesirable growth mode is observed whereby voids form in the Ge next to the SiO 2 and germanide grows over the SiO 2 . A model is proposed in which Ge is the dominant diffusing species during germanidation in the presence of topographies with Ge/SiO 2 boundaries. This undesirable growth is suppressed by the use of a 2-RTA process, preferably involving an RTA1 at ∼250°C, followed by a selective etch of the unreacted Ni, and an RTA2 at ∼330°C.

High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants

Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF₂, resulting in a significant <i>I</i> _ON boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for <i>I</i> _ON by 50%, maintaining similar <i>I</i> _OFF, as measured at the source.

Scaling to Sub- 1 nm Equivalent Oxide Thickness with Hafnium Oxide Deposited by Atomic Layer Deposition

The implementation of HfO 2 gate dielectrics in sub-45 nm devices requires optimization of nanometer-thin HfO 2 layers, deposited, e.g., by atomic layer deposition (ALD). In this work, we optimize ALD conditions such as precursor pulse time and deposition temperature for HfO 2 layers with physical thicknesses below 2 nm. Additionally, we investigate intermediate treatments in the ALD reaction cycle, such as exposure to gas-phase moisture or remote plasma at low temperature and thermal anneals. Such intermediate treatments affect both growth-per-cycle (GPC) and Cl-impurity content of the HfO 2 layers. The analysis of the process modifications allows a better understanding of the reaction mechanisms. H 2 O pulse times of 10 s must be applied to achieve saturation in GPC and Cl content. Using saturated H 2 O pulses decreases the gate leakage current in the sub-1 nm equivalent oxide thickness (EOT) range. The GPC is enhanced from ∼1.8 Hf/nm 2 for conventional ALD to 4 Hf/nm 2 for intermediate plasma treatments at low temperature. Intermediate anneals reduce the Cl content by about two orders of magnitude. Sufficient hydroxylation of the HfO 2 surface is one important factor controlling electrical properties in the sub-1 nm EOT range. The reduction of the Cl content does not systematically improve the electrical properties.

Temperature measurements of polyimide during KrF excimer laser ablation

The temperature at the interface between a thin polyimide film and a quartz substrate was monitored as a function of time during KrF (248 nm) laser‐induced heating and ablation using thin film NiSi thermistors. These experimental temperature measurements were coupled with heat flow simulations to obtain time‐resolved temperature profiles in the polyimide. Thermal properties of the polyimide were estimated by requiring that the simulations reproduce experimental temperature profiles. The peak surface temperature of the polyimide at the onset of ablation was subsequently estimated from these constrained simulations and a value of 1660±100 K was obtained for the observed ablation threshold fluence of 36 mJ/cm2.

Materials and electrical characterization of molecular beam deposited CeO2 and CeO2/HfO2 bilayers on germanium

Properties of CeO2 and CeO2/HfO2 bilayers grown by molecular beam deposition on in situ prepared, oxide-free Ge(100) surfaces are reported here. Deposition is achieved by a simultaneous flux of electron-beam evaporated metal (Ce or Hf) and of remote plasma generated atomic oxygen. These conditions result in an interfacial layer (IL) between the cubic CeO2 and Ge substrate. Electron energy loss spectroscopy shows that this IL is comprised of Ge and O and a small amount of Ce, and x-ray photoelectron spectroscopy suggests that the Ge is in a mix of 2+ and 3+ oxidation states. A comparison of capacitance, conductance, and leakage data shows a higher quality dielectric for 225 °C deposition than for room temperature. However, CeO2-only deposition results in an unacceptably high leakage current due to the small CeO2 band gap, which is remedied by the use of CeO2/HfO2 bilayers. Using the Nicollian–Goetzberger method, interface trap densities in the mid 1011 eV−1 cm−2 are obtained for CeO2/HfO2 gate stacks on bo...