Matty Caymax

Deposition of HfO2 on germanium and the impact of surface pretreatments

The deposition behavior of HfO2 by metalorganic chemical vapor deposition on germanium has been investigated. HfO2 films can be deposited on Ge with equally good quality as compared to high-k growth on silicon. Surface preparation is very important: compared to an HF-last, NH3 pretreatments result in smoother films with strongly reduced diffusion of germanium in the HfO2 film, resulting in a much better electrical performance. We clearly show that much thinner interfacial layers can be obtained, approximately half the thickness of what is typically found for depositions on silicon, suggesting the possibility of more aggressive equivalent oxide thickness∕leakage scaling.

Electrical Properties of III-V/Oxide Interfaces

The great technological achievements of the Silicon Metal-Oxide-Semiconductor (MOS) system were possible because of the very good electrical quality of the Si-SiO2 interface. H-passivation of dangling bonds at the latter interface can result in interface state densities lower than 10 eVcm. As Si CMOS scaling now slowly approaches the atomic length scale, an extension of the technology roadmap might be possible by replacing the Si with alternative substrates with higher mobility. For nMOS, III-V materials seem to be good candidates, because of their high electron mobility. Unfortunately, III-V/oxide interfaces are not quite as robust as the Si-SiO2 interface and most interfaces present high densities of interface states. In the present contribution we analyze GaAs and InGaAs interfaces. Several characterization methods such as the photoluminescence intensity method and the conductance method at high and /or low substrate temperatures are used to characterize the interface state distribution of several III-V interfaces. The interface state distributions of GaAs and In0.53Ga0.47As interfaces with amorphous high-k oxides are presented. These distributions are, as opposed to Si, characterized by localized peaks in the bandgap, which leads to some difficulties for the different characterization techniques. For GaAs, all amorphous oxide interfaces show two very large and localized peaks at around mid-gap energies. Whereas the interface state density closer to the band edges can be reduced with (NH4)2S-cleaning and Hpassivation, the large mid-gap peaks can not be successfully suppressed using these techniques. As a consequence GaAs-amorphous oxide interfaces can not be inverted. For In0.53Ga0.47As, the interface states show a very asymmetric distribution, with reasonably low density close to the conduction band and a very strong increase of interface state density towards the valence band (Figure 1). The consequences of this distribution are discussed in terms of band bending coupling ratio, the ability to control the band bending at the oxide-semiconductor interface, and the performance of the corresponding nMOSFET devices.

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

This paper shows, for the first time, the successful introduction of recessed, strained Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions of pMOS MuGFET devices, improving the on-state current of these devices by 25%, at a fixed off-state condition. The improvement is shown to be a combined effect of compressive stress introduced along the channel, and of a reduced series resistance.

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs

HfO/sub 2/ nMOSFETs and pMOSFETs were fabricated using scaled chemical oxides as a starting interface, together with sputtered (PVD) TiN gate electrodes. Aggressively scaled stacks of 8.2 /spl Aring/ EOT on nMOS and 7.5 /spl Aring/ EOT on pMOS were achieved with leakage current of <5 A/cm/sup 2/ at V/sub FB/ +1 volts. Low fixed charge density in the HfO/sub 2/ layer was observed from VFB extraction, using high frequency-CV measurements, when considering a TiN workfunction of 4.78 eV. Conventional C-V hysteresis and transient V/sub T/ instability measurements on sub 1 nm TiN/HfO/sub 2/ devices indicated reduced instability as a result of EOT scaling. The electron mobility is degraded with EOT scaling whereas hole mobility remains constant down to an EOT of 8 /spl Aring/.

Germanium MOSFETs With

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm²/Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec

\hbox{CeO}_{2}/\hbox{HfO}_{2}/ \hbox{TiN}

The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO/sub 2/ as the gate dielectric. Replacement of SiO/sub 2/ with a high dielectric constant material allows an increase in the physical oxide thickness, while maintaining a low equivalent oxide thickness (EOT) and low direct tunnelling current. The high-k gate dielectric of choice will most likely be a deposited film, which makes the replacement of SiO/sub 2/, a thermally grown layer, even more challenging. Atomic layer CVD (ALCVD/sup TM/) is a well-controlled surface saturating process using gas-solid interactions to deposit thin films. The technique results in covalent bonding between the gaseous precursors and the surface bonding sites. ALCVD/sup TM/ provides highly uniform layers and the possibility to deposit many materials, including mixed oxide layers and nano-laminates. Some of the challenges facing high-k materials include achieving a high quality Si/high-k interface, film stability and solving reliability and integration issues. In this paper, we use MOS capacitors to investigate these challenges for Al/sub 2/O/sub 3/-TiN and Al/sub 2/O/sub 3/-ZrO/sub 2/-TiN gate stacks.

Gate Stacks

Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual...

Electrical characterisation of high-k materials prepared by atomic layer CVD

To boost MOS transistor performance, thickness of the gate dielectric is continuously scaled down. This results in an increase of gate tunneling leakage current, which at some point prevents further downscaling. Desired parameters of alternative materials to SiO 2 are a higher dielectric constant (high-k materials), stability, and compatibility with silicon. A general observation for one of the prime candidates. HfO 2 , is formation of an interfacial layer between the silicon and the high-k material that limits scalability because of its low k-value. Hence, a thorough study of the formation of this layer and its contribution to the equivalent oxide thickness is of utmost importance. We studied the composition and growth kinetics of the interfacial layer formed during the deposition of HfO 2 by metallorganic chemical vapor deposition using O 2 and tetrakis-diethylamidohafnium as precursor. We found the composition and thickness of the interfacial layer to be dependent on the deposition parameters as well as on the starting surface. The layers composition is hafnium silicate-like and its thickness increases as a function of deposition time and temperature. It is therefore controlled by deposition of the HfO 2 layer.

Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

Alternative high-k materials are being researched for future dielectrics in various complementary metal oxide semiconductor applications. We report on the aqueous chemical solution deposition technique as an alternative material screening technique. We used ZrO2 as a reference material to explore the effect of different process parameters on the electrical performance of Pt-dot capacitors. We studied the effects of varying the molar ratio between citric acid and the Zr ions, as well as the conditions of the oxidizing postdeposition anneal. We found that proper optimization of these parameters can significantly reduce the amount of carbon in the layers and enhance the electrical performance of the films to similar levels as atomic layer deposition.

Composition and Growth Kinetics of the Interfacial Layer for MOCVD HfO2 Layers on Si Substrates

This paper describes the fabrication and results of the electrical characterization of buried channel Si/SiGe pMOS devices using double and single quantum wells. The devices have been fabricated in an almost standard CMOS technology including shallow trench isolation, rapid thermal annealing, and standard Co/Ti silicidation. The incorporation of 15% and 32% channels provides a strong enhancement (up to 85%) in long-channel mobility. This increased mobility behavior is translated into a 55% higher on-state current for the long-channel devices and a 13% higher on-state current (V/sub gs/-V/sub T/= -1 V and V/sub ds/= -1.5 V) for devices down to L/sub mask/=70 nm while maintaining low leakage and good short-channel and drain induced barrier lowering behavior.