David P. Nackashi

Nanocell logic gates for molecular computing

Molecular electronics seeks to build electrical devices to implement computation - logic and memory - using individual or small collections of molecules. These devices have the potential to reduce device size and fabrication costs, by several orders of magnitude, relative to conventional CMOS. However, the construction of a practical molecular computer will require the molecular switches and their related interconnect technologies to behave as large-scale diverse logic, with input/output wires scaled to molecular dimensions. It is unclear whether it is necessary or even. possible to control the precise regular placement and interconnection of these diminutive molecular systems. This paper describes genetic algorithm-based simulations of molecular device structures in a nanocell where placement and connectivity of the internal molecular switches are not specifically directed and the internal topology is generally disordered. With some simplifying assumptions, these results show that it is possible to use easily fabricated nanocells as logic devices by setting the internal molecular switch states after the topological molecular assembly is complete. Simulated logic devices include an inverter, a NAND gate, an XOR gate and a 1-bit adder. Issues of defect and fault tolerance are addressed.

Controllable molecular modulation of conductivity in silicon-based devices.

The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to gating and impurity doping. Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted molecular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal-oxide-semiconductor field-effect transistors (pseudo-MOSFETs). The molecular effects can even penetrate through a 4.92-mum thick silicon layer. Our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes.

Scaling constraints in nanoelectronic random-access memories

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.

Molectronics: a circuit design perspective

Recently, several mechanisms have been proposed as a basis for designing molecular electronic logic switching elements. Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to silicon devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A series of logic gates and a memory element are simulated based on the voltage-controlled current flow method using the Tour-Reed molecular diode exhibiting negative differential resistance (NDR). HSPICE simulation results are used to illustrate the performance of these devices and to quantify additional component and interconnect requirements. Finally, future system design approaches using molecular components are discussed.

Deterministic nanowire fanout and interconnect without any critical translational alignment

Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Solutions to this problem have generally required either nanoprecision alignment or stochastic assembly. A design is presented that allows complete and deterministic fanout of regular arrays of wires from the nano- to the microworld without the need for any critical translational alignment steps. For example, deterministically connecting 10-nm wires directly to 3-mum wires would require a translational alignment to within only about 6 mum. The design also allows for nanowire interconnect and is independent of the technology used to fabricate the nanowires, enabling technologies for which alignment remains very challenging. The impact of potential fabrication errors is analyzed and a structure is fabricated that demonstrates the feasibility of such a design

Design of rotating MEMS tunable capacitors for use at rf and microwave frequencies

With the recent surge in popularity of RF and Microwave MEMS many different device topologies are being explored. Some devices provide large changes in capacitance, but lack the ability to provide a linear range of capacitance values between the minimum and maximum values of the device. We present a device design for a low-loss rotating MEMS tunable capacitor that once programmed to the required value consumes no power. This device design is transformed from gear structures currently designed in the SUMMiT process with modifications made so that the device may be used as a varactor. Modifications include alterations of physical structure, drive mechanism for programming capacitance value, and additional post processing steps needed to provide low-loss at RF and Microwave frequencies. Many different device structures are possible each with performance, potential reliability, and potential yield trade offs that must be considered. Post processing is required to add metal to provide sufficiently low loss for high quality components. Since device planarity is critical for operation, a novel post-process metal deposition technique for providing low stress metal was concieved. Additional modifications to compensate for polysilicon warpage are considered for future investigation. Simulation results based on high frequency full wave analysis software show a highly linear tuning range and a capacitance ratio approaching 6 to 1. A model is extracted from the scattering parameters provided by HFSS and then various device sizes and topologies are compared.

Molecular Electronics – Devices and Circuits Technology

Molecular electronics has several potential advantages for being of interest as an electronic element. It has small size, typically on the range of a few nm, well below the total size projected for any FET. A second advantage is that molecules can self assemble onto surfaces, a very low-cost process. Their third advantage is that they can be designed at the atomic level, a feat not possible with bulk devices. Atomic level design permits a wide range of devices to be investigated, and potentially leads to precise control of electronic properties. For example, switching between isomers of the same chemistry should lead to radically different device properties.

An integrated self-masking technique for providing low-loss metallized RF MEMS devices in a polysilicon only MEMS process (Invited Paper)

A novel masking technique that enables the complex patterning of metal on any layer of a released MEMS chip is demonstrated. This technique enables a polysilicon only MEMS process to create low-loss RF devices. To illustrate the advantages of post-release metallization, in a polysilicon only MEMS process, a rotating MEMS tunable capacitor that provides a wide and linear tuning range is presented. The core of the design comes from high yield, mechanically proven gear designs from Sandia’s SUMMiT design library. Significant alterations were made to the gear structure to create the final device. Preliminary tests show device capacitance ratios of 1.8:1, with linear tuning. Increased metal deposition to reduce the device air gap, can produce a capacitance ratio over 6:1.