Neil Di Spigna

Controllable molecular modulation of conductivity in silicon-based devices.

The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to gating and impurity doping. Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted molecular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal-oxide-semiconductor field-effect transistors (pseudo-MOSFETs). The molecular effects can even penetrate through a 4.92-mum thick silicon layer. Our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes.

Scaling constraints in nanoelectronic random-access memories

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.

Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation

Dual floating gate flash memory has been fabricated and characterized to show dynamic operation, non-volatile operation, and simultaneous dynamic and non-volatile operation. The gate stack consists of a thin dielectric separating two floating gates sandwiched between a tunnel dielectric and interpoly dielectric. The quality of the thin dielectric that separates the floating gates is of utmost importance to retain dynamic operation. In this letter, we investigate a dual floating gate memory transistor and show its potential to combine DRAM and flash functionality in the same device.

A novel double floating-gate unified memory device

A novel double floating-gate unified memory device is experimentally demonstrated for the first time. The device can be used to store both volatile and nonvolatile memory states simultaneously. Simulations of scaled devices show that the device offers several advantages compared to conventional memory devices. Such a device could have a dramatic impact on next generation memory architectures.

Investigation of intermediate dielectric for dual floating gate MOSFET

A dual floating gate transistor offers potential as a unified memory, with simultaneous volatile and non-volatile storage. The quality of the dielectric between the two floating gates is critical to achieving the required dynamic cycle endurance. This paper reports on the results of early experiments into the material choice and process for this dielectric.

Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only)

New architectures for the switch box and connection block are proposed for use in an energy efficient field programmable gate array (FPGA) with bidirectional wiring. Power-hungry SRAMs are replaced by non-volatile nanocrystal floating gate (NCFG) devices that retain their state while the system power is off and do not need to be configured at boot up. The NCFG-based FPGA is benchmarked against both a traditional bidirectional and a modern unidirectional SRAM-based FPGA using a 32-tap FIR Filter designed in HSPICE based on predictive BSIM4.0 CMOS with 45nm gate length technology and a previously developed physical model of the NCFG device. Compared to the traditional bidirectional and the modern unidirectional SRAM-based interconnect the total gate area is reduced by 87% and 63%, respectively. Simulations demonstrate a reduction of 58% in static and 34% in dynamic power consumption compared to the traditional bidirectional SRAM-based FPGA while the signal propagation delay through a switch box is decreased by 28%. When compared to the modern unidirectional SRAM-based FPGA the proposed design has roughly comparable power consumption but the circuit complexity is greatly reduced as a result of doubling the available routing channels. Alternatively the number of the routing channels may be reduced to save area and power whereas the complexity remains similar. The potential benefits from choosing the proposed design can be summarized as small area, low power consumption, high speed and high functionality, which typically trade off and cannot be achieved by the SRAM-based counterparts simultaneously. Compared to previous designs that use continuous floating gate devices in FPGAs, the approach described in this work requires less overhead, lower voltages, and offers improved reliability.

Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates

The operation of a novel unified memory device using two floating-gates is described through experimental characterization of a fabricated proof-of-concept device and confirmed through simulation. The dynamic, nonvolatile, and concurrent modes of the device are described in detail. Simulations show that the device compares favorably to conventional memory devices. Applications enabled by this unified memory device are discussed, highlighting the dramatic impact this device could have on next generation memory architectures.