Douglas E. Loy

Low-temperature amorphous-silicon backplane technology development for flexible displays in a manufacturing pilot-line environment

— A low-temperature amorphous-silicon (a-Si:H) thin-film-transistor (TFT) backplane technology for high-information-content flexible displays has been developed. Backplanes were integrated with frontplane technologies to produce high-performance active-matrix reflective electrophoretic ink, reflective cholesteric liquid crystal and emissive OLED flexible-display technology demonstrators (TDs). Backplanes up to 4 in. on the diagonal have been fabricated on a 6-in. wafer-scale pilot line. The critical steps in the evolution of backplane technology, from qualification of baseline low-temperature (180°C) a-Si:H process on the 6-in. line with rigid substrates, to transferring the process to flexible plastic and flexible stainless-steel substrates, to form factor scale-up of the TFT arrays, and finally manufacturing scale-up to a Gen 2 (370 × 470 mm) display-scale pilot line, will be reviewed.

30.2: Active Matrix Electrophoretic Displays on Temporary Bonded Stainless Steel Substrates with 180 °C a‐Si:H TFTs

A low temperature, 180 °C, amorphous Si (a-Si:H) process on bonded stainless steel substrates is discussed and a 3.8-inch QVGA active matrix (AM) electrophoretic display as well as a 64×64 electrophoretic display with integrated column drivers are demonstrated. The n-channel thin-film transistors (TFTs) exhibited saturation mobilities of 0.7 cm2/V-sec, median drive currents of 26.2 μA and low defectivity.

Amorphous Silicon Thin-Film Transistor Backplanes Deposited at 200

The transition of thin-film transistor (TFT) backplanes from rigid plate glass to flexible substrates requires the development of a generic TFT backplane technology on a clear plastic substrate. To be sufficiently stable under bias stress, amorphous-silicon (a-Si:H) TFTs must be deposited at elevated temperatures, therefore the substrate must withstand high temperatures. We fabricated a-Si:H TFT backplanes on a clear plastic substrate at 200degC. The measured stability of the TFTs under gate bias stress was superior to TFTs fabricated at 150degC. The substrate was dimensionally stable within the measurement resolution of 1, allowing for well-aligned 8 times 8 and 32 times 32 arrays of pixels. The operation of the backplane is demonstrated with an electrophoretic display. This result is a step toward the drop-in replacement of glass substrates by plastic foil.

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The U.S. Army, Arizona State University (ASU) and commercial industry have joined forces to create the Flexible Display Center (FDC) at Arizona State University, a large-scale collaborative venture designed to rapidly advance flexible display technology to the brink of commercialization. The Center has completed its startup phase and is now engaged in an intensive and aggressive applied research and development program that will produce high quality, high performance active matrix reflective and emissive flexible display technology demonstrators (TDs). Electrophoretic ink and cholesteric liquid crystals have been selected as Center reflective imaging layer technologies; these technologies are attractive because they are fully reflective and bistable (extremely low power) and because the materials are environmentally robust and intrinsically rugged. Organic light emitting devices (OLEDs) have been chosen as the emissive imaging layer technology. These three electro-optic subsystems will be integrated with a flexible a-Si thin film transistor active matrix backplane platform. We have created the integrated design, backplane fabrication, display assembly, test and evaluation capability to enable rapid cycles of learning and technology development. Backplane fabrication is currently accomplished on a 6” wafer scale pilot line linked to a Manufacturing Execution System and supported by a comprehensive suite of in-fab metrology tools. We are currently installing a GEN II pilot line, with qualified operation slated for 2006. This line will be used to demonstrate process and display form factor capability, while providing high yield low volume manufacturing of pilot-scale levels of technology demonstrators for the Army and our commercial partners.

on Clear Plastic for Lamination to Electrophoretic Displays

In this paper we describe solutions to effectively address critical challenges in direct fabrication of amorphous silicon thin film transistor (TFTs) arrays for active matrix flexible displays. For both metal foil and plastic flexible substrates a manufacturable handling protocol in automated display-scale equipment is required. We have successfully demonstrated a temporary bonding protocol that required development of new enabling materials, tools and processes. For metal foil substrates, the principal challenges are planarization and electrical isolation, and management of stress (CTE mismatch) during TFT fabrication. For plastic substrates, the principal challenges are dimensional instability management in conjunction with manufacturing-ready temporary adhesives. Solutions required a systems-level approach to address the challenges of the substrates and their handling simultaneously.

Flexible reflective and emissive display integration and manufacturing

Principal challenges to direct fabrication of high performance a-Si:H transistor arrays on flexible substrates include automated handling through bonding-debonding processes, substrate-compatible low temperature fabrication processes, management of dimensional instability of plastic substrates, and planarization and management of CTE mismatch for stainless steel foils. In collaboration with our industrial and academic partners, we have developed viable solutions to address these challenges, as described in this paper.