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Dive into the research topics where David Stephen Levitan is active.

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Featured researches published by David Stephen Levitan.


Ibm Journal of Research and Development | 2015

Advanced features in IBM POWER8 systems

Balaram Sinharoy; Randal C. Swanberg; Naresh Nayar; Bruce Mealey; Jeffrey A. Stuecheli; Berni Schiefer; Jens Leenstra; J. Jann; Philipp Oehler; David Stephen Levitan; Susan E. Eisen; D. Sanner; Thomas Pflueger; Cedric Lichtenau; William E. Hall; T. Block

The IBM POWER8™ processor includes many innovative features that enable efficient and flexible computing, along with enhancements in virtualization, security, and serviceability. These features benefit application performance, and big data and analytics computing, as well as the cloud environment. Notable features include the capabilities to dynamically and efficiently change the number of threads active on a processor, enhancing application performance via integer vector operations, encryption accelerations, and reference history arrays. Also notable is improved virtual machine density (supporting multiple simultaneous partitions per core and providing fine-grain power management), allowing continuous monitoring of system performance as well as significantly enhanced system RAS (reliability, availability, and serviceability) and security. Each of these features is technologically complex and advanced. This paper provides an in-depth description of some of these features and their exploitation through systems software and middleware. These features will continue to bring value to the system-of-record workloads in the enterprise. They also make POWER8 systems well-suited for serving the needs of newer workloads such as big data and analytics, while efficiently supporting deployment in cloud environments.


Archive | 1998

Self-checking content-addressable memory and method of operation for detecting multiple selected word lines

David Stephen Levitan


Archive | 2003

Split branch history tables and count cache for simultaneous multithreading

Gregory W. Alexander; Scott Bruce Frommer; David Stephen Levitan; Balaram Sinharoy


Archive | 1998

Pipelined two-cycle branch target address cache

Brian R. Konigsburg; David Stephen Levitan


Archive | 2005

Branch encoding before instruction cache write

Brian R. Konigsburg; Hung Qui Le; David Stephen Levitan; John Wesley Ward


Archive | 1998

Method for updating a branch history table in a processor which resolves multiple branches in a single cycle

David Stephen Levitan


Archive | 2005

Method and logical apparatus for managing processing system resource use for speculative execution

Lee Evan Eisen; David Stephen Levitan; Francis Patrick O'Connell; Wolfram Sauer


Archive | 1997

Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages

David Stephen Levitan; John Stephen Muhich


Archive | 1999

Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache

David Stephen Levitan; Shashank Nemawarkar; Balaram Sinharoy; William J. Starke


Archive | 1999

Method and system for software control of hardware branch prediction mechanism in a data processor

Robert William Hay; James Allan Kahle; Brian R. Konigsburg; David Stephen Levitan; Balaram Sinharoy

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