Gregory W. Alexander

Split branch history tables and count cache for simultaneous multithreading

Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache

Enhanced STCX design to improve subsequent load efficiency

COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Dual-issuance of microprocessor instructions using dual dependency matrices

Method and system for handling cache coherency for self-modifying code

Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions