Wolfram Sauer

IBM POWER6 microarchitecture

This paper describes the implementation of the IBM POWER6™ microprocessor, a two-way simultaneous multithreaded (SMT) dual-core chip whose key features include binary compatibility with IBM POWER5™ microprocessor-based systems; increased functional capabilities, such as decimal floating-point and vector multimedia extensions; significant reliability, availability, and serviceability enhancements; and robust scalability with up to 64 physical processors. Based on a new industry-leading high-frequency core architecture with enhanced SMT and driven by a high-throughput symmetric multiprocessing (SMP) cache and memory subsystem, the POWER6 chip achieves a significant performance boost compared with its predecessor, the POWER5 chip. Key extensions to the coherence protocol enable POWER6 microprocessor-based systems to achieve better SMP scalability while enabling reductions in system packaging complexity and cost.

IBM POWER6 reliability

This paper describes the state-of-the art reliability features of the IBM POWER6™ microprocessor. The POWER6 microprocessor includes a high degree of detection of soft and hard errors in both dataflow and control logic, as well as a feature--instruction retry recovery (IRR)--usually available only on mainframe systems. IRR provides full hardware error recovery of those registers that are defined by the instruction set architecture. This is accomplished by taking a checkpoint of the defined state for both of the core threads and recovering the machine state back to a known good point. To allow changing memory accessibility without using different page table entries, the POWER6 microprocessor implements virtual page class keys, a new architectural extension that enables the OS (operating system) to manage eight classes of memory with efficiently modifiable access authority for each class. With this feature, malfunctioning kernel extensions can be prevented from destroying OS data that may, in turn, bring an OS down.

A 1.8-GHz instruction window buffer for an out-of-order microprocessor core

To address the challenges in microprocessor designs beyond a gigahertz, an instruction window buffer (IWB) was designed. The IWB implements the processor parts for renaming, reservation station, and reorder buffer as a unified buffer. Measured results on an experimental chip demonstrated operation of the IWB macros supporting 1.8 GHz, with the chip being at the fast end of the process distribution. The technology is 0.18-/spl mu/m CMOS8S bulk technology with seven levels of copper interconnect and a 1.5-V supply voltage.

IBM POWER6 partition mobility: moving virtual servers seamlessly between physical systems

This paper presents the IBM Power Architecture™ extension for enhanced virtualization that is first implemented in the POWER6™ processor. Virtual partition memory enables all of the memory of a virtual server running in a logical partition to be made virtual by the POWER Hypervisor™ firmware. The Processor Compatibility register allows backward compatibility by providing a mode in which a POWER6 processor behaves like a POWER5™ processor. Enhancements to the timebase facility enable updates to the virtual timebase of a logical partition while maintaining consistency with other partitions in the system. These fundamental enhancements are explained and their role in implementing the new partition mobility junction is described. Partition mobility allows the seamless migration of virtual servers from one physical POWER6 microprocessor-based system to another.

Instruction translation for an experimental S/390 processor

The IBM™ S/390™ architecture is a complex architecture, which has grown over a long period of time. Typical implementations use microcode to cope with the more complex instructions and facilities of S/390. Current IBM S/390 processors even contain two levels of microcode.We report on an experimental S/390 processor based on a RISC processor kernel employing superscalar, out of order execution of instructions. S/390 instructions have to be translated into internal sequences of RISC instructions. Actually two closely coupled internal sequences - one for register based execution and one for storage based execution are generated. The translation is a straight-forward mapping in most cases with some flexibility for special instructions.The paper introduces the hardware mechanisms used for mapping S/390 instructions to internal sequences. The facilities, which provide a greater degree of flexibility are discussed. The interactions of the low-level mapping scheme with the microcode levels is examined. Finally we discuss our experiences with this type of implementation of a CISC architecture on a RISC processor kernel.