David Su

Recent advances in electron tomography: TEM and HAADF-STEM tomography for materials science and semiconductor applications.

Electron tomography is a well-established technique for three-dimensional structure determination of (almost) amorphous specimens in life sciences applications. With the recent advances in nanotechnology and the semiconductor industry, there is also an increasing need for high-resolution three-dimensional (3D) structural information in physical sciences. In this article, we evaluate the capabilities and limitations of transmission electron microscopy (TEM) and high-angle-annular-dark-field scanning transmission electron microscopy (HAADF-STEM) tomography for the 3D structural characterization of partially crystalline to highly crystalline materials. Our analysis of catalysts, a hydrogen storage material, and different semiconductor devices shows that features with a diameter as small as 1-2 nm can be resolved in three dimensions by electron tomography. For partially crystalline materials with small single crystalline domains, bright-field TEM tomography provides reliable 3D structural information. HAADF-STEM tomography is more versatile and can also be used for high-resolution 3D imaging of highly crystalline materials such as semiconductor devices.

The study of sensitive circuit and layout for CDM improvement

The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.

Solid-State Reaction in an Au Wire Connection with an Al-Cu Pad During Aging

In integrated-circuit packages, wire-bonding techniques are the preferred methods for making electrical connections between the chip and the lead frame. The influence of aging at 150°C up to 3,000 hr on interfacial reactions of Au wire bonded with the Al-Cu pad was investigated herein. To observe various intermetallic compounds (IMCs) with field-emission scanning electron microscopy, polished samples were ion-milled through precision etching and coating techniques. Three IMCs, i.e., (Al,Cu)Au4, (Al,Cu)3Au8, and (Al,Cu)Au2, were found between the Au wire and the Al-Cu pad in the as-assembled wire bond. After 168 hr of aging, Al3(Au,Cu)8 formed between (Al,Cu)3Au8 and (Al,Cu)Au2 in the center of the wire bond. In fact, the Al-Cu pad, (Al,Cu)Au2, and Al3(Au,Cu)8 IMCs were completely reacted after 500 hr of aging. (Al,Cu)3)Au8 was thus transformed into (Al,Cu)Au4. Near the edge of the wire bonds, (Al,Cu)Au2 formed between the Al-Cu pad and (Al,Cu)3Au8 during 500 hr of aging. For aging longer than 1000 hr, Al3(Au,Cu)8 was detected between (Al,Cu)3Au8 and (Al,Cu)Au2. It was noted that the Al3(Au,Cu)8 IMC gradually grew with aging. With the aid of microstructure evolution and quantitative analysis, the interfacial phase transformation between the Au wire and the Al-Cu pad could be probed. In addition, the growth kinetics of (Al,Cu)Au4 and (Al,Cu)3Au8 in the center of wire bonds were also evaluated and discussed.

Application of secondary electron potential contrast on junction leakage isolation

Secondary electron potential contrast (SEPC) technology with an in situ dynamic trigger was studied to inspect P+/N-well junction leakage arising from P-well misalignment in a static random access memory cell. Combining SEPC with scanning electron microscopy observations allows direct identification of the junction shift. Furthermore, an in situ negative bias applied to the P-well can create a wider depletion region and eliminate the leakage path in P+/N-well contacts, allowing the P+/N well to operate normally. This proposed in situ dynamic trigger method is a promising and effective approach to investigating device physics under a dynamic scope.

The mechanism of device damage during bump process for flip-chip package

Ring-type yield loss at wafer edge has been observed during flip-chip packaging process. The failure mechanism is attributed to the scrubber clean process step which generates a lot of charges. This in turn behaves like an electrostatic discharge (ESD) event and damages gate oxide of internal circuits. An equivalent circuit is proposed to analyze such a kind of ESD event and proves the importance of the parasitic capacitance of the interconnect metal.

Surface potential and electric field mapping of p-well/n-well junction by secondary electron potential contrast and in-situ nanoprobe biasing

This study investigates the p-well/n-well junction by using secondary electron potential contrast (SEPC) with in-situ nanoprobe biasing. Experimental result demonstrated dopant contrast is restored after applying electricity in the junction nodes. Furthermore, the image contrast was converted to a voltage scale, allowing the junction surface potential and electric filed distribution to be identified. The proposed method demonstrates that an in-situ nanoprobe system is powerful in dopant area inspection in SEM, potentially contributing to an efficient method in analyzing site-specific failure in real circuits.

A new ESD model induced yield loss during chip-on-film package process and it's failure mechanism

A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism of COF package induced yield loss has been identified. Two factors dominate the yield loss. One is the ESD generation on the tape surface during COF tape reeled out process. The other one is the required high temperature for the inner lead bonding, which lowers the breakdown voltage of the gate oxide. As a result, an IC might be damaged to induce the yield loss.

The effect of geometry in the characterization of barrier profile in vias by transmission electron microscopy

Characterization of the profile and thickness of barrier layers in cylindrical vias by cross-sectional transmission electron microscopy (TEM) is crucial for understanding the behavior of Cu interconnects and is becoming a challenge for the 0.13 /spl mu/m node and below. In this study, we demonstrate how the geometry of the TEM sample affects the contrast of the barrier layer and propose guidelines for TEM sample preparation and image interpretation.