David V. Campbell

Novel self-stressing test structures for realistic high-frequency reliability characterization

A series of self-stressing test structures suitable for investigation of reliability failure mechanisms (hot carriers, electromigration, oxide breakdown) under realistic integrated circuit operating conditions, is described. These structures contain DC-controlled, high-frequency on-chip oscillators, which stress test structures. As a result, high-frequency (>200-MHz) stress-testing can be performed using less expensive DC test systems. In particular, hot-carrier stress-testing was performed at frequencies up to 230 MHz, which is the highest stress frequency reported for inverters. For the 1- mu m technology examined, the quasi-static model accurately describes the degradation. The statistical variation in high-frequency, hot-carrier-induced degradation is presented, and variations with temperature are shown to be consistent with DC stress results. Since only DC test systems are needed, these structures provide a simple method to calibrate reliability simulators and characterize high-frequency reliability effects.<<ETX>>

High-brightness, high-spatial-resolution, 6.151keV x-ray imaging of inertial confinement fusion capsule implosion and complex hydrodynamics experiments on Sandia’s Z accelerator (invited)

When used for the production of an x-ray imaging backlighter source on Sandia National Laboratories’ 20MA, 100ns rise-time Z accelerator [M. K. Matzen et al., Phys. Plasmas 12, 055503 (2005)], the terawatt-class, multikilojoule, 526.57nm Z-Beamlet laser (ZBL) [P. K. Rambo et al., Appl. Opt. 44, 2421 (2005)], in conjunction with the 6.151keV, Mn–Heα curved-crystal imager [D. B. Sinars et al., Rev. Sci. Instrum. 75, 3672 (2004)], is capable of providing a high quality x radiograph per Z shot for various high-energy-density physics experiments. Enhancements to this imaging system during 2005 have led to the capture of inertial confinement fusion capsule implosion and complex hydrodynamics images of significantly higher quality. The three main improvements, all leading effectively to enhanced image plane brightness, were bringing the source inside the Rowland circle to approximately double the collection solid angle, replacing direct exposure film with Fuji BAS-TR2025 image plate (read with a Fuji BAS-5000 sc...

Process characterization vehicles for 3D Integration

Assemblies produced by 3D Integration, whether fabricated at die or wafer level, involve a large number of post fab processing steps. Performing the prove-in of these operations on high value product has many limitations. This work uses simple surrogate process characterization vehicles, which workaround limitations of cost, timeliness of piecparts, ability to consider multiple processing options, and insufficient volumes for adequately exercising flows to collect specific process data for characterization. The test structures easily adapt to specific product in terms of die dimensions, aspect ratios, pitch and number of interconnects, and etc. This results in good fidelity in exercising product-specific processing. The discussed Cyclops vehicle implements a mirrored layout suitable for stacking to itself by wafer-to-wafer, die-to-wafer, or die-to-die. A standardized 2×10 pad test interface allows characterization of any of the integration methods with a single simple setup. This design offers the utility of comparison study of the various methods all using the same basis.

Self-stressing structures for electromigration testing to 500 MHz

We demonstrate for the first time high frequency (500 MHz) electromigration at the wafer-level using on-chip, self-stressing test structures. Since the stress temperature, frequency, duty cycle and current are controlled by DC signals in these structures, we used conventional DC test equipment without any special modifications (such as high frequency cabling, high temperature probe cards, etc.). This structure significantly reduces the cost of performing realistic high frequency electromigration experiments.<<ETX>>

High-frequency Test Structures For Wafer-level Reliability

A series of unique self-stressing reliability test structures suitable for investigation of reliability concerns (hot carriers, electromigration, oxide breakdown) under realistic integrated circuit operating conditions are reported. These structures contain on-chip voltage-controlled oscillators. Using only DC signals, high-frequency (>lo0 MHz with nanosecond rise and fall times) wafer-level reliability characterizations are performed. This work describes these self-stressing structures with an example of a high-frequency, hot-carrier degradation performed at the wafer-level.