David Wei Zhang

Tunable Charge-Trap Memory Based on Few-Layer MoS2

Charge-trap memory with high-κ dielectric materials is considered to be a promising candidate for next-generation memory devices. Ultrathin layered two-dimensional (2D) materials like graphene and MoS2 have been receiving much attention because of their fantastic physical properties and potential applications in electronic devices. Here, we report on a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. Because of the extraordinary trapping ability of both electrons and holes in HfO2, the MoS2 memory device exhibits an unprecedented memory window exceeding 20 V. Importantly, with a back gate the window size can be effectively tuned from 15.6 to 21 V; the program/erase current ratio can reach up to 10(4), allowing for multibit information storage. Moreover, the device shows a high endurance of hundreds of cycles and a stable retention of ∼ 28% charge loss after 10 years, which is drastically lower than ever reported MoS2 flash memory. The combination of 2D materials with traditional high-κ charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.

Characterization of atomic-layer-deposited Al2O3∕GaAs interface improved by NH3 plasma pretreatment

Al2O3 thin films were deposited by atomic layer deposition on HF-cleaned and NH3 plasma-treated GaAs surfaces, respectively. The precursors used for Al2O3 films are trimethylaluminum and water. Effects of NH3 plasma pretreatment on the electrical and structural properties of Al2O3∕GaAs interface were investigated by C-V measurements, high-resolution transmission electron microscopy, and x-ray photoelectron spectroscopy measurements. The C-V measurements showed that the electrical property is improved after NH3 plasma pretreatment. X-ray photo electron spectroscopy analyses confirmed that GaAs oxides and elemental As are greatly decreased and the GaAs surface can be efficiently protected during NH3 plasma pretreatment and atomic layer deposition of Al2O3.

The mechanism of the asymmetric SET and RESET speed of graphene oxide based flexible resistive switching memories

Oxygen migration is reported as key factors of resistive switching in graphene oxide (GO) based memories by different groups. A flexible nonvolatile resistive switching memory based on GO was fabricated through a spin-coating process. The speed of the SET and RESET operations of the GO memories was found to be significant asymmetric. The RESET speed is in the order of 100 ns under a −5 V voltage while the SET speed is three orders of magnitude slower (100 μs) under a 5 V bias. The behavior of resistive switching speed difference is elucidated by voltage modulated oxygen diffusion barrier change.

Optical investigation of reduced graphene oxide by spectroscopic ellipsometry and the band-gap tuning

Spectroscopic ellipsometry was used to characterize the optical response of few layer reduced graphene oxide and graphene oxide in visible range. Lorentz oscillator model is added to analyze the ellipsometric parameters. The experiment shows the optical response of few layer reduced graphene oxide and monolayer exfoliated graphene in visible range is quite similar with slight difference due to the structure defects. The Lorentz oscillator model gives experimental support to investigate the band-gap tuning through the reduction process in details.

Highly Uniform Bipolar Resistive Switching With

The bipolar resistive switching characteristics of atomic-layer-deposited NbAlO-based devices have been investigated for nonvolatile memory applications. With the help of a thin Al2O3 buffer layer, highly uniform and reproducible bipolar resistance switching cycles could be observed. Four typical multilevel operations, with resistances being at 1000, 350, 145, and 75 ¿, respectively, are also successfully demonstrated by varying the current compliance during the set process. The resistance ratios of high-resistance state to low-resistance state are more than 103 within 5000 cycles during the test without any degradation. Moreover, the estimated retention lifetime at room temperature is sufficiently long to fulfill the typical ten-year requirement. Considering its excellent memory switching behavior, a resistance switching device composed of a NbAlO film with a thin Al2O3 buffer layer is a possible candidate to be integrated into future memory processes.

\hbox{Al}_{2}\hbox{O}_{3}

In this brief, a novel U-shape-channel tunneling field-effect transistor (UTFET) with a SiGe source region is investigated by 2-D technology computer aided design simulation. The enlarged tunneling area and enhanced tunneling rate dramatically increase the tunneling current when the device is turned on. Meanwhile, the off-leakage current of UTFET is suppressed because of the extended physical channel length. The on-state tunneling current of UTFET can be further improved by introducing an n+-doped Si delta layer under the source region. The inserted delta layer significantly shortens the band-to-band tunneling path, enlarges tunneling area, and thus enhances the tunneling rate of this device. The average value of the subthreshold swing (SS) of the optimized UTFET is 58 mV/dec when VGS is varied from 0 to 0.46 V. Using the SiGe-source UTFET structure with a delta layer, the merits of low leakage current, high drive current, and ultralow SS can be realized simultaneously.

Buffer Layer in Robust NbAlO-Based RRAM

The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm2 at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 108, subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm2/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics.

Design of U-Shape Channel Tunnel FETs With SiGe Source Regions

Faster at the Gate Advanced designs will be needed to continue to improve the performance of the main components of high-speed computing, metal-oxide semiconductor field-effect transistors (MOSFETs) and floating-gate (FG) MOSFETs. Wang et al. (p. 640) fabricated a semi-floating gate (SFG) transistor in which a tunneling field-effect transistor couples the positively doped floating gate to the negatively doped drain region. The charge stored on the SFG was used to shift the voltage threshold for switching the transistor, which in turn sped up its operation and lowered the power consumed. These devices were used for ultrahigh-speed memory and in light sensing and imaging. An embedded tunneling field-effect transistor speeds switching by varying the voltage threshold of the main gate electrode. As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

Atomic-layer-deposited Al2O3–HfO2–Al2O3 dielectrics have been investigated to replace conventional silicon oxide and nitride for radio frequency and analog metal-insulator-metal capacitors applications. In the case of 1‐nm‐Al2O3, sufficiently good electrical performances are achieved, including a high dielectric constant of ∼17, a small dissipation factor of 0.018 at 100kHz, an extremely low leakage current of 7.8×10−9A∕cm2 at 1MV∕cm and 125°C, perfect voltage coefficients of capacitance (74ppm∕V2 and 10ppm∕V). The quadratic voltage coefficient of capacitance decreases with the applied frequency due to the change of relaxation time with different carrier mobility in insulator, and correlates with the dielectric composition and thickness, which is of intrinsic property owing to electric field polarization. Furthermore, the conduction mechanism of the AHA dielectrics is also discussed, indicating the Schottky emission dominated at room temperature.

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

Thin NiO films are grown at 300 ° C on Si (100) using atomic layer deposition. The dependence of annealing temperature on the optical properties of NiO films has been investigated using spectroscopic ellipsometry in the spectral region of 1.24 – 5.05 eV . It is found that the refractive index and thickness of NiO films are affected by high temperature annealing. The optical band gap of the as-deposited thin NiO film is determined to be 3.8 eV , which is almost independent of the annealing temperature. The indirect band gap of NiO film shifts toward lower photon energy with an increase in annealing temperature.