David William Goodwin

Automatic generation of application specific processors

An application-specific instruction-set processor (ASIP) is ideally suited for embedded applications that have demanding performance, size, and power requirements that cannot be satisfied by a general purpose processor. ASIPs also have time-to-market and programmability advantages when compared to custom ASICs. The AutoTIE system simplifies the creation of ASIPs by automatically enhancing a base processor with application specific instruction set architecture (ISA) extensions, including instructions, operations, and register files. The new instructions, operations, and register files are automatically recognized and exploited by the entire software tool chain, including the C/C++ compiler. Thus, taking advantage of the generated ASIP does not require any changes to the application or any assembly language coding. AutoTIE uses the C/C++ compiler to analyze an application, and based on the analysis generates thousands, or even millions, of possible ISA extensions for the application. AutoTIE then uses performance and hardware estimation techniques to combine the ISA extensions into a large number of potential ASIPs, and for a range of hardware costs, chooses the ASIP that provides the maximum performance improvement. For example, for an application performing a radix-4 FFT, AutoTIE considers over 34,000 potential sets of ISA extensions. For hardware costs ranging from 7800 gates to 128,000 gates, AutoTIE combines these extensions to form 31 ASIPs, which provide performance improvements ranging from a factor of 1.12 to a factor of 11.3 compared to a general-purpose processor.

Configurable Multi-Processor Platforms for Next Generation Embedded Systems

Next-generation embedded systems in application domains such as multimedia, wired and wireless communications, and multipurpose portable devices, are increasingly turning to multiprocessor platforms as a vehicle for their realization. But entirely fixed platforms composed of entirely fixed components lack the flexibility and ability to be optimized to the application to offer the best solution in any of these areas. Configurability at multiple levels offers a much better chance to optimize the resulting multiprocessor platform. Existing and emerging technologies for configurable and extensible processors and the creation of configurable multiprocessor subsystem platforms offer significant capability to design teams to both differentiate and optimize their products.

Automated Processor Configuration and Instruction Extension

Publisher Summary The application-specific instruction-set processor (ASIP) concept is reviewed in this chapter and discusses automated processor configuration. Tailoring a processor to an application has been more of an art than an exact science, and the process demands effort when done on a manual ad hoc basis. Many existing approaches to ASIP creation require the in-depth knowledge of a processor architect, the software knowledge of applications specialists, and the hardware-implementation skills of a team of experienced digital designers. Both structural, coarse-grained configuration parameters (for example, the inclusion or exclusion of functional units, the width of processor-to-memory or bus interfaces, the number and size of local and system memories), and fine-grained instruction extensions (the addition of application-specific tuned instructions that accelerate the processing of major functional application kernels by a factor of 2 ×, 10 ×, and more) are possible in ASIP configuration. Deciding the specific configuration parameters and extended instructions can be akin to finding the optimal needle in the proverbial haystack—and requires years of broad experience in a host of design disciplines. With this in mind, the design and use of ASIPs on a widespread basis across multiple application domains demand a more automated process for creating these processors from high-level configuration specifications.