Davide De Caro

Dual-tree error compensation for high performance fixed-width multipliers

In this paper, a new error-compensation network for fixed-width multipliers is proposed. The error-compensation block is composed of two summation trees which are optimally chosen in order to minimize either the mean-square error or the maximum absolute error. The new technique substantially improves error performances with respect to previously proposed approaches. Simulation results show that new fixed-width multipliers exhibit significant improvements both in propagation delay and in power dissipation with respect to previous solutions.

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches.

Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error

Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, to reduce complexity, and a suitable compensation function is added to partly compensate the introduced error. The optimal compensation function, that minimizes the mean square error, is obtained in this paper in closed-form for the first time. A sub optimal compensation function, best suited for hardware implementation, is introduced. Efficient multipliers implementation based on sub-optimal function is discussed. Proposed truncated multipliers are extensively compared with previously proposed circuits. Experimental results, for a 0.18 μm technology, are also presented.

Direct digital frequency synthesizers with polynomial hyperfolding technique

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique.

A novel high-speed sense-amplifier-based flip-flop

A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.

New clock-gating techniques for low-power flip-flops

Two novel low power flip-flops are presented in the paper. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile. We present the implementation of an all-digital spread spectrum clock generator. The circuit is realized by using a design flow completely based on standard cells and is able to perform clock spreading with an arbitrary modulation profile and a modulation frequency up to 5 MHz. The circuit uses two digitally controlled delay lines driven by a digital modulator to synthesize the output waveform. A replica delay line is employed in a real-time measurement circuit to track process, voltage and temperature variations. A chip has been implemented in a 65 nm CMOS technology. The chip is able to generate signals up to 1.27 GHz. The measured peak level reduction of the clock spectrum, at 750 MHz output frequency, is 20.5 dB with a 6% modulation depth. The power dissipation is 44 mW @ 1.27 GHz.

A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique

The paper presents a detailed description of a direct digital frequency synthesizer (DDFS) based on a Multipartite Table Method (MTM) which is a salient lookup table compression technique. A novel algorithm to find the optimal MTM decomposition which minimizes the ROM size while archiving a target spurious free dynamic range (SFDR) is presented in the paper. The DDFS designed with the proposed technique is ideally suited for a high clock frequency operation, requiring small lookup tables and simple multi-operand adders. Low-power operation is achieved through a power-driven synthesis, by using in the circuit two flip-flop topologies (with different power and delay performances). A test chip has been realized in 0.25 mum, 2.5 V technology. The circuit achieves a 90 dBc SFDR and operates at a maximum clock frequency of 630 MHz, with 76 mW power dissipation. By reducing the power supply at 1.8 V, a maximum operating frequency of 430 MHz was measured, with a total power dissipation as low as 24.9 mW

Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method

The use of the multipartite table methods (MTMs) to implement high-performance direct digital frequency synthesizers (DDFSs) is investigated in this paper. A closed-form expressions for the spurious-free dynamic range (SFDR) is obtained when a single table of offset (TO) is used in the multipartite approximation. In this case, the optimal design that minimizes storage requirement for a given SFDR can be obtained analytically. A numerical algorithm is also presented to obtain the optimal design also when two or more TOs are employed is the approximation. The VLSI implementation results and the comparison with previously proposed DDFS architectures demonstrate the effectiveness of multipartite table methods for the realization of high performance direct digital synthesizers.

A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25

The paper describes the implementation of a 380 MHz, 13 bit, direct digital synthesizer/mixer IC in 0.25mum CMOS technology. The circuit employs an innovative architecture which divides the pi/4 rotation operation required in the quadrature synthesizer/mixers, in three rotations. The first two rotations are implemented by using a CORDIC datapath completely realized in carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation, and a multiply by constant and addition circuit for the second rotation. The final (third) rotation is multiplier-based, in order to reduce the circuit latency and increase the circuit performances. The CORDIC datapath is implemented with a novel approach both at the algorithmic level and at the transistor level. At the algorithmic level the combined employ of sign-extension prevention, overflow prevention and a novel rounding scheme are presented. At the transistor level a design style that jointly uses full-CMOS and DPL to improve the circuit latency is described. The overall circuit performances are very interesting. The synthesizer/mixer IC, realized in a 0.25 mum CMOS technology, has an area occupation of 0.22 mm2 and dissipates 152 mW at 380 MHz with a supply voltage of 2.5 V