Gerardo Castellano

Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs

Approximate computing is emerging as a new paradigm to improve digital circuit performance by relaxing the requirement of performing exact calculations. Approximate adders rely on the idea that for uniformly distributed inputs, long carry-propagation chains are rarely activated. Unfortunately, however, the above assumption on input signal statistics is not always verified; in this paper we focus on the case (often encountered in practical signal processing applications) when the inputs have a Gaussian distribution. We show that for Gaussian inputs the error probability of previously proposed approximate adders approaches 25% for low sigma values, which is much larger than the uniform case. On the basis of this analysis, we propose an approximate adder with a correction circuit that drastically reduces the error rate for Gaussian distributed operand s. In order to investigate the performance of our approach in a real application, simulated results for a simple audio processing system are reported. Implementation results in 65nm technology are also presented.

A low power control system for real-time tuning of a hybrid transformer-based receiver

This paper presents the analysis and hardware implementation of a low-power control system for a frequency-division duplexing 3G receiver with a tunable on-chip duplexer based on a hybrid-transformer. The maximum transmit-receive isolation exceeds 60dB and is limited by the precision of the on-chip balancing impedance. An optimization algorithm finds the optimal duplexer tuning condition in less than 100μs and a simple tracking algorithm operating in background preserves this condition over time. The algorithms are implemented in a FPGA and require minimal hardware overhead.

A 0.7–2 GHz auxiliary receiver with enhanced compression for SAW-less FDD

A wideband auxiliary receiver embeds a band-reject N-path filter in the low-noise amplifier to improve the compression point. The receiver has high input impedance and it can be placed at the transmitter output without loading effects. Implemented in a 28nm CMOS technology it occupies 0.12mm2 active area and it can withstand up to +4 dBm QPSK modulated 20 MHz signal with less than 1-dB noise degradation at 50 MHz offset, achieving an equivalent −171 dBc/Hz noise-to-carrier ratio at 1 GHz. Operation was experimentally verified between 0.7 and 2 GHz. The signal path draws 9 mA from a 1.8 V supply and the clock generation circuits draw 16 mA from a 1.2V supply at 1 GHz.

Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence

The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems only provide white noise sources while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a programmable colored noise generator that, while generating noise signals with features matching the state of the art, overcomes the previously proposed circuits in terms of speed (+10%) and logic resource occupation (-75%).

A SISO Register Circuit Tailored for Input Data with Low Transition Probability

The paper proposes a SISO register circuit, functionally equivalent to a Shift Register, that is the optimal design choice when the input data have a reduced transition probability. The proposed circuit obtains improved performances by only storing the transitions of the input data, thus saving logic and power.

Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise

The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems usually provide white noise sources, while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a filtering circuit and an algorithm to design the same that produces an arbitrary colored electrical noise. The proposed system improves the performances of the previously proposed circuits in terms of spectral characteristics of the output, in terms of logic resource occupation and power dissipation, while providing no penalty on the working frequency.

An Efficient Digital Background Control for Hybrid Transformer-Based Receivers

The design and hardware implementation of a digital control system tailored to a hybrid transformer-based duplexer is proposed. Working at Nyquist sampling frequency, it finds the optimal transmit-receive isolation in about 150

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding

\mu \text{s}

An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands

even when modulated signals with high PAPR (16-QAM) are transmitted. A simple tracking algorithm, operating in background, preserves this condition over time. Uninterrupted system operation can be guaranteed through an auxiliary receiver with sub-mW power dissipation, minimizing the overhead of the entire control system. The algorithms are implemented on FPGA to carry out the experimental validation of the full hardware implementation. Moreover, the hardware overhead of the digital control algorithm is analyzed, synthesizing the digital circuit in 40-nm CMOS technology.

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines

Piecewise polynomial interpolation is a well-established technique for hardware function evaluation. The paper describes a novel technique to minimize polynomial coefficients wordlength with the aim of obtaining either exact or faithful rounding at a reduced hardware cost. The standard approaches employed in literature subdivide the design of piecewise-polynomial interpolators into three steps (coefficients calculation, coefficients quantization and arithmetic hardware optimization) and estimate conservatively the overall approximation error as the sum of the error components arising in each step. The proposed technique, using Integer Linear Programming (ILP), optimizes the polynomial coefficients taking into account all error components simultaneously. This gives two advantages. Firstly, we can obtain exactly rounded approximations; secondly, for faithfully rounded interpolators, we avoid any overdesign due to pessimistic assumptions on error components, optimizing in this way the resulting hardware. The proposed ILP based algorithm requires an acceptable CPU time (from few seconds to tens of minutes) and is suited for approximations up to, maximum, 24 input bits. The results compare favorably with previously published data. We present synthesis results in 28 nm and 90 nm CMOS technologies, to further assess the effectiveness of the proposed approach.