Dean J. Denning

A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >

A high performance 0.5 mu m BiCMOS triple polysilicon technology for 4 Mb fast SRAMs

A high-performance 0.5 mu m BiCMOS technology has been developed which uses a triple polysilicon process architecture for a 4 Mb fast SRAM class of products. Three layers of polysilicon are used to achieve a compact four transistor cell size that is less than 20 mu m/sup 2/ by creating self-aligned bit-sense and Vss contacts to the four transistor cell. A WSi/sub x/ polycide emitter n-p-n transistor has been implemented with an emitter area of 0.8*2.4 mu m/sup 2/ and peak cutoff frequency (f/sub T/) of 14 GHz. A selectively ion implanted collector has been used to compensate the base channeling tail as well as to increase knee current and f/sub T/, while maintaining a collector to emitter breakdown voltage of 6.5 V. A minimum ECL gate delay of 115 ps has been achieved at a gate current of 400 mu A.<<ETX>>

A self-aligned LDD/channel implanted ITLDD process with selectively-deposited poly gates for CMOS VLSI

A novel inverse-T LDD (ITLDD) CMOS process has been developed as part of a submicron CMOS technology that features self-aligned LDD/channel implantation for improved hot-carrier protection. The resulting ITLDD device structures can be designed with very light n- and p-LDD (lightly doped drain) implantations. This leads to lower substrate current due to reduced compensation effects of the lightly doped LDD regions by the heavy channel doping profile. The use of selective polysilicon deposition rather than an incomplete polysilicon etchback process to define the inverse-T gate results in a simpler, more manufacturable process for the ITLDD structure.<<ETX>>

An inlaid CVD Cu based integration for sub 0.25 /spl mu/m technology

This report describes the development and integration of a blanket CVD copper film into advanced microprocessor devices. The in situ deposition of sputtered Tantalum based or CVD Titanium based barrier layers and PVD Cu under and overlayers has been demonstrated to improve film adhesion and device electrical performance.

A 0.20 /spl mu/m CMOS technology with copper-filled contact and local interconnect

In this work a 0.20 /spl mu/m CMOS technology has been developed using copper-filled local interconnect and contact along with copper metallization. This technology is suitable for logic and SRAM applications. The presence of copper in close proximity to the gate oxide and source/drain regions does not induce any degradation to the transistor parameters. This study shows that copper, along with a robust diffusion barrier, can be used to fill local interconnect and contact holes without deteriorating device performance. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.63 /spl mu/m.

A nonrecessed-base, self-aligned bipolar structure with selectively deposited polysilicon emitter

A self-aligned bipolar structure, which features a nonrecessed base and a selectively deposited polysilicon emitter, is proposed. The in situ surface cleaning process prior to the selective-polysilicon deposition minimizes the residual native oxide in the emitter window. Both high-quality selective-polysilicon film and well-behaved submicrometer bipolar device characteristics have been obtained for bipolar or BiCMOS VLSI applications. The effects of the nonrecessed-base device structure on the bipolar device parameter distribution and bipolar hot-carrier immunity are also discussed. >

Selectivity Mechanisms in Low Temperature (<950°C) Selective Silicon Epitaxy

Low temperature selective silicon epitaxy was studied over a range of process pressures and HCI flows using a SiH 2 Cl 2 /HCl/H 2 based chemistry. Thermodynamic modelling was carried out with the aid of the SOLGAS program to investigate the effect of process pressure, HCI flow rate, and leaks on the distribution of gas phase species. Selectivity results are interpreted in terms of the defect microchemistry on SiO 2 surfaces.

Integration Challenges of Inorganic Low-K (K≤2.5) Materials with Cu for Sub-0.25µm Multilevel Interconnects

The recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.

A selectively deposited poly-gate ITLDD process with self-aligned LDD/channel implantation

An inverse-T lightly doped drain (ITLDD) CMOS process which features improved hot-carrier effects and self-aligned source/drain and channel implantation profiles is presented. Compensation effects by the heavy channel doping on the light N/sup -//P/sup -/ profile are minimized in this ITLDD structure, because the implants are self-aligned to the polysilicon-gate edge. In addition, because selective polysilicon deposition rather than an incomplete poly-gate etchback is used to define the ITLDD structure, a simpler, more manufacturable process is obtained due to improved control of the thin poly-gate shelf thickness.<<ETX>>