James D. Hayden

The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p/sup +/ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V/sub FB/, increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF/sub 2/ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi/sub 2/ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO/sub 2//Si interface. >

The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

It is shown that fluorine plays a major role in the penetration of boron into and through the gate oxides of p-channel MOSFETs that use p/sup +/ doped polysilicon gates. Boron penetration results in large positive shifts in V/sub FB/, increased p-channel subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Inclusion of a phosphorus coimplant or TiSi/sub 2/ salicide is shown to minimize this effect. The boron penetration phenomenon is modeled by the creation of a very shallow, fully depleted p-type layer in the silicon substrate close to the SiO/sub 2/-Si interface. Elemental boron is shown to be superior to BF/sub 2/ as an implant species for surface channel submicron PMOS devices.<<ETX>>

Trench isolation for 0.45 /spl mu/m active pitch and below

A trench isolation technology which realizes a 0.45 /spl mu/m active pitch while maintaining latch-up holding voltage above 3.0 V for n+/p+ spaces /spl ges/0.6 /spl mu/m for 0.35 /spl mu/m deep trenches is described. Process optimization yields superior gate oxide (t/sub ox/=55 /spl Aring/) and diode performance comparable to LOCOS type isolations. Inverse narrow width effects are minimal at 30 mV (PMOS) and 100 mV (NMOS) for channel widths down to 0.17 /spl mu/m. Anomalous MOSFET sub-threshold conduction due to field crowding at the active edge has been avoided. The variation of field oxide thickness is 40 nm within a wafer and 10 nm within a 15 mm square die.

Poly-gate sidewall oxidation induced submicrometer MOSFET degradation

The effect of poly-gate sidewall oxidation on short-channel MOSFET behavior is examined. The gain, threshold voltage, and apparent electrical channel length are shown to be very sensitive to the location of the n/sup -/ junction edge with respect to the poly-gate edge for a lightly-doped-drain NMOS transistor. New guidelines for the design of submicrometer MOSFETs based on an analysis of the sidewall oxidation of the polysilicon after gate definition are proposed.<<ETX>>

A comparison of base current reversal and bipolar snapback in advanced n-p-n bipolar transistors

It is argued that base current reversal in an advanced n-p-n bipolar transistor arises from the same physical mechanism as classical bipolar snapback. Measurements of the bipolar snapback voltage, BV/sub CE0/, and of the collector-emitter voltage required for base current reversal, V/sub CE/Br/ are identical over a range of variation in transistor design and over more than eight orders of magnitude in collector current. The minimum or sustaining values of BV/sub CE0/, or V/sub CE/Br/, should be used for the purposes of bipolar device design rather than the larger trigger value measured at very low current levels. The former is an indication of electric field strength in the collector-base depletion region while the latter is a monitor of the level of the nonideal base current component. Measurement of base current reversal provides a more consistent and less destructive technique of characterizing bipolar sustaining voltage.<<ETX>>

A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >

A high performance 0.5 mu m BiCMOS triple polysilicon technology for 4 Mb fast SRAMs

A high-performance 0.5 mu m BiCMOS technology has been developed which uses a triple polysilicon process architecture for a 4 Mb fast SRAM class of products. Three layers of polysilicon are used to achieve a compact four transistor cell size that is less than 20 mu m/sup 2/ by creating self-aligned bit-sense and Vss contacts to the four transistor cell. A WSi/sub x/ polycide emitter n-p-n transistor has been implemented with an emitter area of 0.8*2.4 mu m/sup 2/ and peak cutoff frequency (f/sub T/) of 14 GHz. A selectively ion implanted collector has been used to compensate the base channeling tail as well as to increase knee current and f/sub T/, while maintaining a collector to emitter breakdown voltage of 6.5 V. A minimum ECL gate delay of 115 ps has been achieved at a gate current of 400 mu A.<<ETX>>

A high-performance sub-half micron CMOS technology for fast SRAMs

An advanced high-performance sub-half-micron technology for fast CMOS SRAMs (static RAMs) has been developed. Features of this thin-well process include: an aggressive interwell isolation module, framed-mask poly-buffered LOCOS isolation (FMPBL), a 125-AA gate oxide, dual n/sup +//p/sup +/ implanted polysilicon gates, titanium salicide, two levels of polysilicon, TiN metallization barriers, a poly plug option, and up to three layers of metallization. An interwell isolation process allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m. Active transistor design is optimized to reduce the polysilicon gate birds beak and LDD (lightly doped drain) underdiffusion. Discrete transistor lifetimes for hot carrier degradation are in excess of 10 years of 3.3-V operation. A 16 K*4 SRAM displays no parametric shifts after HCl stressing for 1000 h at 7 V and 0 degrees C. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are obtained.<<ETX>>

Advanced SRAM technology-the race between 4T and 6T cells

This work discusses the trade-offs between 4T SRAM cells which use four bulk transistors (and have poly resistor or TFT loads) and 6T SRAM cells which use six bulk transistors (and use bulk PMOS loads). 4T SRAM cells have dominated the stand-alone SRAM market since first introduced in the 1970s, but 6T SRAM cells have been dominant for on-chip storage in advanced microprocessors and other logic circuits. However, recently there has been a resurgence of interest in 6T cells for stand alone SRAM applications. While 4T cells are typically smaller, they generally require a more complex process, and have poorer stability, especially at low voltage. This paper quantitatively examines several different trade-offs in SRAM cell design.

Reverse short channel effect and channel length dependence of boron penetration in PMOSFETs

The anomalous increase in reverse-short-channel effect of PMOSFETs, in the presence of boron penetration from the gate, is examined here. Based on an extensive simulation and experimental study, we demonstrate that the degree of boron penetration is a function of the channel length and that long channel transistors are more susceptible to boron penetration compared to short channel devices. This leads to the observed decrease in threshold voltage with increasing channel length and hence, an enhanced reverse-short-channel-like behavior in PMOSFETs. Using length scale arguments, we propose that silicon interstitial absorption into the gate oxide is responsible for blocking boron penetration at the edges of the channel as compared to the middle, thus making the short channel length transistors more immune to boron penetration as compared to long channel length ones.