Debasri Saha

SoC: a real platform for IP reuse, IP infringement, and IP protection

Increased design complexity, shrinking design cycle, and low cost--this three-dimensional demandmandates advent of system-onchip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite scattered, limited in possibilities in multithreat environment, and sometimes mutually conflicting. Existing works need critical survey, proper categorization, and summarization to focus on the inherent tradeoff, existing security holes, and new research directions. This paper discusses the IP-based SoC design flow to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringements. It also clearly highlights recent challenges and new opportunities in this emerging field of research.

A Unified Approach for IP Protection across Design Phases in a Packaged Chip

IP values contributed by the distinct design tools in specific design phases, are recognized by observing the signature of the owner of each tool as functional or scan mode output of the fabricated chip, for certain input vector secret to the owner. An existing approach inserts watermark through reordering of single scan chain, and solely identifies the owner of the logic design tool. Here we propose a novel scheme to watermark the recent reconfigurable scan architectures, operating in both scan tree and single scan mode. The signature of the owner of physical design tool along with that of logic design tool can separately be embedded while designing the scan tree and also verified from the packaged chip without conflict using two distinct modes. A bi-objective minimization of overhead in routing and power is supported through our scheme. Experimental results on design overhead and robustness for ISCAS’89 benchmarks are encouraging.

Robust intellectual property protection of VLSI physical design

In deep sub-micron VLSI, increased demand for design productivity of ICs with millions of devices has led to widespread design reuse. This however enhances the probability of infringement of intellectual property (IP) of the design. Typically, repudiation attack by the IP owner through challenging the legality of the buyer and additive attack through insertion of additional marks in the design are not considered in the design cycle. Moreover, public watermark verification is still not secure, as attacker manages to override the mark with his own one. Our proposed algorithm ROBUST_IP tackles these issues with a modified IP marking schema. Firstly, it introduces a master key of an independent intellectual property protection (IPP) team to eliminate the scope of repudiation attack, renders insertion of fake marks useless and can efficiently extract the signatures of legal IP owner and buyer in absence of any claim. Secondly, the concept of a new parameter, public_verification_count, enhances security during public mark verification. Finally, novel techniques based on this schema are proposed to embed marks in the physical design phase specifically for ASIC and FPGA design. Experimental results on MCNC benchmarks demonstrate that removal/tampering of marks remain infeasible at the cost of insignificant overhead in area/delay.

RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks

With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH) remain dormant during the testing phase but get triggered at runtime and threaten the integrity and confidentiality of the chip. In this paper, we focus on threat to confidentiality. HTH threatens the confidentiality of such chips by leaking the secret information at runtime. We propose an intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially. Low area and low power overhead of our proposed RTNA on practical crypto SOC architectures as obtained in the experimental results confirm its practical implementation. Hardware implementation of trust generation at runtime, use of unsupervised learning and use of an intelligent architecture are the novelties of this work.

Encoding of Floorplans through Deterministic Perturbation

Recent trends in VLSI design involve rapid growth of design reuse and electronic Intellectual Property (IP) commerce. For VLSI physical design, the risk of misappropriation of design IP stored in design repositories, or the threat of hacking the same during its web-based transmission, mandates design file encryption. However, encryption of GDSII/OASIS design files, too large in size and complex in format, is troublesome, time consuming and also prone to typical cryptanalysis. The idea of an alternate efficient approach of encoding by deterministic perturbation of design IP resulting in a degraded design of negligible IP value, is proposed here to ensure security during design storage or transmission. From the highly degraded design only authorized person can quickly regenerate the optimized design. In this paper, the technique for design encoding through perturbation is applied for floorplanning stage. Encoding moves for various floorplan representations are analyzed and a novel technique for encoding tree-based representations is proposed. Experimental results on floorplan perturbation for MCNC benchmarks are encouraging.

A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection

The emerging trend of design reuse in VLSI circuits poses the threat of theft and misappropriation of intellectual property (IP) of the design. Protection of design IP is a matter of prime concern today. We propose a scheme SECURE_IP, which tackles the problem from an entirely new viewpoint. It relies on the application of cryptographic principles and the watermarking techniques to provide both direct and indirect IP protection in VLSI physical design. It makes unauthorized disclosure of a valuable design infeasible during its transmission, and can easily detect any alteration of the design file during transmission. The proposed scheme ensures authentication of the original designer as well as non-repudiation between the designer (seller) and the buyer. Illegal reselling can be efficiently detected by the proposed scheme. The algorithm SECURE_IP is tested on random and MCNC benchmark instances, and the experimental results are quite encouraging

Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design

Reuse of Intellectual Property (IP) of VLSI physical design facilitates integration of more components on a single chip in shrinking time-to-market. For intellectual property protection (IPP), various kinds of IP marks are embedded into the design for establishing the veracity of a legal owner. However, public verification of IP marks is not leakage-proof. Current techniques include a sufficiently large set of public marks containing a header and a message body in addition to private ones to facilitate only public verification at the cost of significant increase in design overhead. But these techniques are not effective, as attackers manage to obtain potential clues to tamper public marks rendering public verification invalid and may also suitably override the marks to include own signature resulting in wrong public identification of IP owner. Here we propose a zero-knowledge protocol to ensure robust and absolutely leakage proof convincing public verification with the help of private marks. We have tested our protocol for FPGA benchmarks. The results on overhead and robustness are encouraging.

FPGA-Based IP and SoC Security

Intellectual property (IP) cores in FPGAs are being used widely as these provide high flexibility and efficiency at low cost and low time-to-market. An IP in FPGA is primarily a HDL design or a bitfile for the same. Security aspects have specific issues for the FPGA IP cores. Partial recon gurability of an FPGA has introduced further security holes. A bitfile or a partial bitstream is loaded on an FPGA architecture in encrypted form in order to prevent unauthorized access of the IP. This encryption of the bitfile may be cracked through side-channel attacks. For authentication of a genuine IP vendor and an authorized IP user, their binary signatures may be included in the FPGA bitstream. However, maintaining resilience of the signatures against tampering is a challenge in case of their public verification. Another recent challenge in FPGAs due to hardware Trojans or extraneous circuitry inserted surreptitiously is being combated with parity-based detection techniques. However, it is still hard for the standard FPGA tools to detect Trojan circuits inserted directly in the bitfile cores. In case of a system-on-a-chip (SoC) implemented with FPGAs, the security issues in IP distribution, IP management, and inter-communication are even more complex and challenging. This chapter elaborates the various security techniques adopted in FPGAs, security measures remain as research proposal, along with several alarming security threats open for research.

Coherence based dual microphone speech enhancement technique using FPGA

Abstract This paper, presents a design and implementation of dual microphone coherence based speech enhancement technique using field programmable gate array (FPGA). In order to have a proper enhancement of dual microphone system, we require to estimate the time delay of arrival (TDOA) between the two microphone signals which is followed by the application of the proposed speech enhancement algorithm. We have used TDOA algorithm based on phase transform to minimize the effect of reverberation for localization of the sound sources. Coherence based technique has been used for speech enhancement process which requires no background noise estimation. In this way, we can achieve a high localization accuracy and also the capability of dealing with coherent noise. In the proposed system, TDOA and speech enhancement processes are executed concurrently exploiting the parallel logic blocks of FPGA, thus increasing the throughput of the system to a great extent. We have implemented our design on Spartan6 Lx45 FPGA device. The subjective evaluation of the proposed design with normal hearing listeners using comprehensibility listing test has been done and its performance has been compared to the existing state of the art research works. The objective evaluation of the proposed design also designates the significant melioration over the existing state of the art research works. The subjective and objective evaluation infer that our proposed hardware induce feasible solution for hearing aid and other hand-held devices.

Analysis of Secret Key Revealing Trojan Using Path Delay Analysis for Some Cryptocores

The design outsourcing of the IC supply chain across the globe has been witnessed as a major trend of the semiconductor design industry in the recent era. The increasing profit margin has been a major boost for this trend. However, the vulnerability of the introduction of malicious circuitry (Hardware Trojan Horses) in the untrusted phases of chip development has been a major deterrent in this cost effective design methodology. Analysis, detection and correction of such Trojan Horses have been the point of focus among researchers over the recent years. In this work, analysis of a secret key revealing Hardware Trojan Horse is performed. This Trojan Horse creates a conditional path delay to the resultant output of the cryptocore according to the stolen bit of secret key per iteration. The work has been extended from the RTL design stage to the pre fabrication stage of ASIC platform where area and power analysis have been made to distinguish the affected core from a normal core in 180nm technology node.