Susmita Sur-Kolay

A modeling approach for addressing power supply switching noise related failures of integrated circuits

Power density of high-end microprocessors has been increasing by approximately 80% per technology generation, while the voltage is scaling by a factor of 0.8. This leads to 225% increase in current per unit area in successive generation of technologies. The cost of maintaining the same IR drop becomes too high. This leads to compromise in power delivery and power grid becomes a performance limiter. Traditional performance related test techniques with transition and path delay fault models focus on testing the logic but not the power delivery. In this paper we view power grid as performance limiter and develop a fault model to address the problem of vector generation for delay faults arising out of power delivery problems. A fault extraction methodology applied to a microprocessor design block is explained.

Floorplanning for Partially Reconfigurable FPGAs

Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced by fixing the position and shapes of modules common across all instances. We propose a global floorplan generation method PartialHeteroFP to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal. Experimental results establish that the proposed PartialHeteroFP produces floorplans very fast, with 100% match of common modules and thereby minimizing the partial reconfiguration overhead.

Energy-Efficient Long-term Continuous Personal Health Monitoring

Continuous health monitoring using wireless body area networks of implantable and wearable medical devices (IWMDs) is envisioned as a transformative approach to healthcare. Rapid advances in biomedical sensors, low-power electronics, and wireless communications have brought this vision to the verge of reality. However, key challenges still remain to be addressed. The constrained sizes of IWMDs imply that they are designed with very limited processing, storage, and battery capacities. Therefore, there is a very strong need for efficiency in data collection, analysis, storage, and communication. In this paper, we first quantify the energy and storage requirements of a continuous personal health monitoring system that uses eight biomedical sensors: (1) heart rate, (2) blood pressure, (3) oxygen saturation, (4) body temperature, (5) blood glucose, (6) accelerometer, (7) electrocardiogram (ECG), and (8) electroencephalogram (EEG). Our analysis suggests that there exists a significant gap between the energy and storage requirements for long-term continuous monitoring and the capabilities of current devices. To enable energy-efficient continuous health monitoring, we propose schemes for sample aggregation, anomaly-driven transmission, and compressive sensing to reduce the overheads of wirelessly transmitting, storing, and encrypting/authenticating the data. We evaluate these techniques and demonstrate that they result in two to three orders-of-magnitude improvements in energy and storage requirements, and can help realize the potential of long-term continuous health monitoring.

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare

Machine learning is being used in a wide range of application domains to discover patterns in large datasets. Increasingly, the results of machine learning drive critical decisions in applications related to healthcare and biomedicine. Such health-related applications are often sensitive, and thus, any security breach would be catastrophic. Naturally, the integrity of the results computed by machine learning is of great importance. Recent research has shown that some machine-learning algorithms can be compromised by augmenting their training datasets with malicious data, leading to a new class of attacks called poisoning attacks. Hindrance of a diagnosis may have life-threatening consequences and could cause distrust. On the other hand, not only may a false diagnosis prompt users to distrust the machine-learning algorithm and even abandon the entire system but also such a false positive classification may cause patient distress. In this paper, we present a systematic, algorithm-independent approach for mounting poisoning attacks across a wide range of machine-learning algorithms and healthcare datasets. The proposed attack procedure generates input data, which, when added to the training set, can either cause the results of machine learning to have targeted errors (e.g., increase the likelihood of classification into a specific class), or simply introduce arbitrary errors (incorrect classification). These attacks may be applied to both fixed and evolving datasets. They can be applied even when only statistics of the training dataset are available or, in some cases, even without access to the training dataset, although at a lower efficacy. We establish the effectiveness of the proposed attacks using a suite of six machine-learning algorithms and five healthcare datasets. Finally, we present countermeasures against the proposed generic attacks that are based on tracking and detecting deviations in various accuracy metrics, and benchmark their effectiveness.

The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order

Channel graphs for nonsliceable floorplans are studied for determination of feasible channel routing order. The minimum feedback vertex set (MFVS) formulation is revisited and a polynomial time heuristic is presented. It is shown that feasible routing orders with reserved channels, L-channels, and monotone channels can be obtained from a given MFVS for any floorplan. This approach provides a powerful tool to unify all three previous approaches and produces a solution with comparable efficiency and quality.<<ETX>>

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis

Quantum circuits consist of a cascade of quantum gates. In a physical design-unaware quantum logic circuit, a gate is assumed to operate on an arbitrary set of quantum bits (qubits), without considering the physical location of the qubits. However, in reality, physical qubits have to be placed on a grid. Each node of the grid represents a qubit. The grid implements the architecture of the quantum computer. A physical constraint often imposed is that quantum gates can only operate on adjacent qubits on the grid. Hence, a communication channel needs to be built if the qubits in the logical circuit are not adjacent. In this paper, we introduce a tool called the physical design-aware fault-tolerant quantum circuit synthesis (PAQCS). It contains two algorithms: one for physical qubit placement and another for routing of communications. With the help of these two algorithms, the overhead of converting a logical to a physical circuit is reduced by 30.1%, on an average, relative to previous work. The optimization algorithms in PAQCS are evaluated on circuits implemented using quantum operations supported by two different quantum physical machine descriptions and three quantum error-correcting codes. They reduce the number of primitive operations by 11.5%-68.6%, and the number of execution cycles by 16.9%-59.4%.

Fsimac: a fault simulator for asynchronous sequential circuits

At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper presents Fsimac, a gate-level fault simulator for stuck-at and gate-delay faults in asynchronous sequential circuits. Fsimac not only evaluates combinational logic and typical asynchronous gates such as Muller C-elements, but also complex domino gates, which are widely used in high-speed designs. Our algorithm for desecting feedback loops is designed so as to minimize the iterations for simulating the unfolded circuit. We use min-max timing analysis to compute the bounds on the signal delays. Stuck-at faults are detected by comparing logic values at the primary outputs against the corresponding values in the fault-free design. For delay faults, we additionally compare min-max rime stamps for primary output signals. Fault coverage reported by Fsimac for pseudo-random tests generated by Cellular Automata show some very good results, but also indicate test holes for which more specific patterns are needed. We intend to deploy Fsimac for designing more effective CA-BIST.

Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs

Recent field-programmable gate array (FPGA) architectures are heterogeneous, owing to the presence of millions of gates in configurable logic blocks (CLBs), block RAMs, and multiplier blocks (MULs) which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithms for application-specific integrated circuits (ASIC) do not suffice. In this paper, we propose a three-phase algorithm for unified floorplan-topology generation and sizing on heterogeneous FPGAs. The method consists of a recursive balanced bipartitioning followed by the generation of slicing topologies and finally the allocation of CLBs and RAM/MULs to modules by a greedy heuristic and minimum-cost maximum-flow method, respectively. Experimental results on benchmark circuits show that our method HeteroFloorplan produces feasible floorplans within a few seconds with total half-perimeter wirelength (HPWL) improvement of 18%-52% over the very few previous approaches. We also compare our locally greedy CLB allocation with a network-flow formulation to establish its effectiveness.

Synthesis Techniques for Ternary Quantum Logic

Synthesis of ternary quantum circuits involves basic ternary gates and logic operations in the ternary quantum domain. Works that define ternary algebra and their applications for ternary quantum logic realization, are very few. In this paper, we express a ternary logic function in terms of projection operations including a new one. We demonstrate how to realize a few new multi-qutrit ternary gates in terms of generalized ternary gates and projection operations. We then employ our synthesis method to design ternary adder circuits which have better cost than that obtained by earlier method.

Efficient Algorithms for Vertex Arboricity of Planar Graphs

Acyclic-coloring of a graph G = (V,E) is a partitioning of V, such that the induced subgraph of each partition is acyclic. The minimum number of such partitions of V is defined as the vertex arboricity of G. A linear time algorithm for acyclic-coloring of planar graphs with 3 colors is presented. Next, an O(n2) algorithm is proposed which produces a valid acyclic-2-coloring of a planar graph, if one exists, since there are planar graphs with arboricity 3.