Debjyoti Bhattacharjee

Delay-optimal technology mapping for in-memory computing using ReRAM devices

Recent propositions of diverse In-Memory Computing platforms have shown a promising alternative to classical Von Neumann computing models. Significant benefits, in terms of energy-efficiency and performance, are reported for in-memory arithmetic circuits, neural networks, CAM, cache hierarchy and even fully programmable processors. In contrast, design automation tools supporting the development of such designs are still in a nascent phase. By leveraging the native stateful logic operation capability of ReRAM devices, several logic synthesis flows have been reported. In this paper, we complement these flows with a detailed study on the technology mapping phase for ReRAM devices. We provide a delay-optimal solution for technology mapping without area constraint and propose further heuristics to achieve device count reduction and to support delay optimization under the constraint of parallel instruction dispatch. We report at least 3× less delay compared to the naïve technology mapping adopted in recent studies. The proposed heuristics achieve 56% on average reduction in device count. Finally, a range of performance trade-offs is identified by applying the constraint of parallel instruction dispatch without noticeable degradation of delay.

ReVAMP: ReRAM based VLIW architecture for in-memory computing

With diverse types of emerging devices offering simultaneous capability of storage and logic operations, researchers have proposed novel platforms that promise gains in energy-efficiency. Such platforms can be classified into two domains — application-specific and general-purpose. The application-specific in-memory computing platforms include machine learning accelerators, arithmetic units, and Content Addressable Memory (CAM)-based structures. On the other hand, the general-purpose computing platforms stem from the idea that several in-memory computing logic devices do support a universal set of Boolean logic operation and therefore, can be used for mapping arbitrary Boolean functions efficiently. In this direction, so far, researchers have concentrated on challenges in logic synthesis (e.g. depth optimization), and technology mapping (e.g. device count reduction). The important problem of efficient technology mapping of arbitrary logic network onto a crossbar array structure has been overlooked so far. In this paper, we propose, ReVAMP, a general-purpose computing platform based on Resistive RAM crossbar array, which exploits the parallelism in computing multiple logic operations in the same word. Further, we study the problem of instruction generation and scheduling for such a platform. We benchmark the performance of ReVAMP with respect to the state of the art architecture.

Multi-valued and fuzzy logic realization using TaOx memristive devices

Among emerging non-volatile storage technologies, redox-based resistive switching Random Access Memory (ReRAM) is a prominent one. The realization of Boolean logic functionalities using ReRAM adds an extra edge to this technology. Recently, 7-state ReRAM devices were used to realize ternary arithmetic circuits, which opens up the computing space beyond traditional binary values. In this manuscript, we report realization of multi-valued and fuzzy logic operators with a representative application using ReRAM devices. Multi-valued logic (MVL), such as Łukasiewicz logic generalizes Boolean logic by allowing more than two truth values. MVL also permits operations on fuzzy sets, where, in contrast to standard crisp logic, an element is permitted to have a degree of membership to a given set. Fuzzy operations generally model human reasoning better than Boolean logic operations, which is predominant in current computing technologies. When the available information for the modelling of a system is imprecise and incomplete, fuzzy logic provides an excellent framework for the system design. Practical applications of fuzzy logic include, industrial control systems, robotics, and in general, design of expert systems through knowledge-based reasoning. Our experimental results show, for the first time, that it is possible to model fuzzy logic natively using multi-state memristive devices.

Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar Arrays

Fast downscaling of technology features in CMOS fabrication processes have resulted in numerous insurmountablechallenges, which prompted researchers to explore alternativestorage and computing technologies. Resistive RAM (ReRAM) isa promising non-volatile storage technology with high endurance, high retention capacity and compatibility with CMOS manufacturing flow. More importantly, ReRAM devices exhibit capability to perform logic operations and therefore, provides an excellent platform for in-memory computing paradigm. Several prominent arithmetic and data analytic applications have been mapped on ReRAM crossbar array so far. Along this line of research, we undertake, for the first time, the mapping of binary-valued matrix-vector operations for ReRAM crossbar array. These linear algebra operations form the key component of diverse applications ranging from graph mining, image processing to bio-informatics. We perform detailed design exploration to obtain an efficient mapping, demonstrate the working flow and finally, present the impact of crossbar dimensions on performance.

Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays

Memristive devices, such as ReRAMs, are fast gaining prominence for their low leakage power, high endurance and non-volatile storage capabilities. ReRAM crossbar arrays also found usage as platform for in-memory computing, particularly for data-intensive computations, due to its inherent capability to perform stateful logic operations. Binary matrix and vector operations arise in several applications that require close interaction with the storage, such as Error Correction Codes (ECC), approximate graph mining, and in general, diverse big data applications. In this paper, we explore for the first time, an efficient mapping of Binary Basic Linear Algebra Subprograms (BiBLAS) onto hybrid CMOS-ReRAM crossbar array. We investigate the impact of crossbar configurations on the delay, and area of BiBLAS operations for various vector sizes.

Efficient Hardware Accelerator for AEGIS-128 Authenticated Encryption

Security of transaction is of paramount importance in modern world of ubiquitous computing and data movement. To provide a framework of standard authenticated encryption techniques, CAESAR contest has been announced recently. Multiple entries in this contest are based on AES, which has been also, a popular choice as a primitive for authenticated encryption in the past. In this paper, we perform in-depth study of efficient hardware implementation for AES-based AEGIS-128 authenticated encryption, a prominent entry in the CAESAR contest. Through a complete study of possible throughput-area improvement techniques, we report multiple design points ranging from a high throughput of \(121.07\) Gbps design to a low-area implementation of \(18.72\) KGE, using commercial synthesis flows and 65 nm ASIC technology. We believe our results will serve as important design metric for the CAESAR contest as well as for efficient AEGIS-128 deployment.

Area-constrained technology mapping for in-memory computing using ReRAM devices

In-memory computing platforms, such as Resistive RAM (ReRAM), offer natural advantage to data-intensive applications. The benefits of data locality and capability to perform native Boolean operations is exploited for significant performance advantage in multiple contexts ranging across neuromorphic computing, associative memory-based computing, arithmetic benchmarks and general-purpose programmable logic-in-memory computing. Despite these advances, design automation tools supporting in-memory computing are still in a nascent phase. In this work, we investigate for the first time, the problem of minimizing delay under arbitrary area constraint of ReRAM devices. We formulate the problem of area-constrained delay minimization as an Integer Linear Programming (ILP) formulation and further propose heuristics that offers scalability as well as solution close to optimal performance. Area-constrained mapping technology mappings enables unlocking significantly large design space trade-offs.

Efficient complementary resistive switch-based crossbar array Booth multiplier

Recent advances of memristive devices allow high endurance, non-volatile storage and low leakage power. Thus, these devices are suitable candidates for in-memory computing. Several recent studies explored the usage of memristive crossbar array for approximate and neuromorphic computing, including approximate matrix-vector multiplication. However, accurate digital circuit realization using device-level simulation, accounting for more realistic ReRAM device behavior, is only studied for adder circuits so far. In this paper, we report the first study of a multiplier scheme with complementary resistive switch-based crossbar arrays. An efficient mapping of Booth multiplication algorithm with different area-timing trade-offs, is discussed. Simulation studies are performed using 4-bit numbers to validate our approach.

In-Memory Data Compression Using ReRAMs

Data compression is a key building block in the current age of information deluge. It is necessary for efficient storage management, effective utilization of communication bandwidth and eventually helps to refine the data to provide information and knowledge. Given the growth of sensors and connected devices, the role of compression in data management is growing in importance steadily. Following the earliest computing abstractions, data is transferred between storage and computing blocks. Any form of processing, including the compression, needs to be run in the computing segment, and returned back to the storage. This basic notion is challenged by the advent of several new technologies, which support logic operations and storage on the same device. Consequently, in-memory computing platforms are being studied by researchers and commercial entities for their applicability in different scenarios, such as data encryption and on-chip machine learning. This chapter explores the implementation of data compression algorithm using such an in-memory computing platform. We explain the building blocks of the in-memory computing architecture, the steps of a data compression algorithm and show step-by-step the mapping process.

Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays

Memristive devices have been shown to have low leakage power, non-volatile storage capability and high storage density. In addition, by using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer functionalities such as arithmetic operations, which make them ideal target for in-memory computing. Multiplexers are useful circuits that are used in a wide variety of applications such as encoding-decoding, signal routing, data communications and data bus control. In this paper, we report the first study on implementation of multiplexers using 1S1R crossbar arrays. An efficient mapping of the multiplexers is presented, with logarithmic delay, in terms of number of control signals — n. Physics-based circuit simulations are performed to validate our approach.