Anne Siemon

Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices

Highly accurate and predictive models of resistive switching devices are needed to enable future memory and logic design. Widely used is the memristive modeling approach considering resistive switches as dynamical systems. Here we introduce three evaluation criteria for memristor models, checking for plausibility of the I-V characteristics, the presence of a sufficiently nonlinearity of the switching kinetics, and the feasibility of predicting the behavior of two antiserially connected devices correctly. We analyzed two classes of models: the first class comprises common linear memristor models and the second class widely used nonlinear memristive models. The linear memristor models are based on Strukovs initial memristor model extended by different window functions, while the nonlinear models include Picketts physics-based memristor model and models derived thereof. This study reveals lacking predictivity of the first class of models, independent of the applied window function. Only the physics-based model is able to fulfill most of the basic evaluation criteria.

A Complementary Resistive Switch-Based Crossbar Array Adder

Redox-based resistive switching devices (ReRAM) are an emerging class of nonvolatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic “sneak” currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al.

Simulation of TaO x -based complementary resistive switches by a physics-based memristive model

Highly predictive memristive models of resistive switches are required to simulate the behavior of anti-serially connected resistive switches, so called complementary resistive switches (CRSs). As an emerging non-volatile device suited for ultra-dense memory architectures, CRS cells offer great potential also as content addressable memories. Here, we introduce a circuit model for TaOx-based resistive switches which we implemented in VerilogA. This model is capable of predicting CRS behavior correctly.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Low-current operations in 4F(2)-compatible Ta2O5-based complementary resistive switches.

Complementary resistive switches (CRS), which consist of two anti-serially connected bipolar switching ReRAM cells, can reduce sneak path currents in passive crossbar arrays. However, the high operation current restrains the implementation of the CRS device. In this article, we present low current operation (<300 μA) of vertically stacked, 4F(2)-compatible Ta2O5-based CRS devices exhibiting two terminals. Two types of devices, either offering a nano- or a micrometer scale bottom cell (BC), are considered. The top cell (TC) in both configurations is designed of micrometer size. A novel three-step electroforming procedure for the vertical CRS device having no access to the middle electrode is exemplified and compared to the conventional forming procedure using three-terminal CRS devices. This three-step electroforming procedure provides adjustment of the maximum switching current in the nano-BC CRS: a low-level current compliance during forming enables low current CRS operation in subsequent switching cycles. Further, the nano-BC CRS shows the stable switching up to 10(4) cycles whereas the micro-BC CRS endures up to 10(6) cycles.

TheProgrammable Logic-in-Memory(PLiM) Computer

Realization of logic and storage operations in memristive circuits have opened up a promising research direction of in-memory computing. Elementary digital circuits, e.g., Boolean arithmetic circuits, can be economically realized within memristive circuits with a limited performance overhead as compared to the standard computation paradigms. This paper takes a major step along this direction by proposing a fully-programmable in-memory computing system. In particular, we address, for the first time, the question of controlling the in-memory computation, by proposing a lightweight unit managing the operations performed on a memristive array. Assembly-level programming abstraction is achieved by a natively-implemented majority and complement operator. This platform enables diverse sets of applications to be ported with little effort. As a case study, we present a standardized symmetric-key cipher for lightweight security applications. The detailed system design flow and simulation results with accurate device models are reported validating the approach.

Efficient complementary resistive switch-based crossbar array Booth multiplier

Recent advances of memristive devices allow high endurance, non-volatile storage and low leakage power. Thus, these devices are suitable candidates for in-memory computing. Several recent studies explored the usage of memristive crossbar array for approximate and neuromorphic computing, including approximate matrix-vector multiplication. However, accurate digital circuit realization using device-level simulation, accounting for more realistic ReRAM device behavior, is only studied for adder circuits so far. In this paper, we report the first study of a multiplier scheme with complementary resistive switch-based crossbar arrays. An efficient mapping of Booth multiplication algorithm with different area-timing trade-offs, is discussed. Simulation studies are performed using 4-bit numbers to validate our approach.

Study of Memristive Associative Capacitive Networks for CAM Applications

Resistively switching devices are key enabler for future hybrid CMOS/nano-crossbar array architectures. Due to the availability of nonvolatile states novel reconfigurable in-memory computing approaches become feasible. In particular complementary resistive switches are highly attractive cross-point junction elements due to their inherent sneak path prevention. By applying a nondestructive capacitive readout procedure the complementary resistive switches implement reconfigurable associative capacitive networks. Those networks establish the functionality of content addressable memories and enable memory intensive computing operations for realization of pattern recognition tasks. These are essential for router or network switch applications. In this study a highly accurate physics-based dynamical memristive device model is used to evaluate the network properties for various configurations. The high ON-to-OFF ratio of electrochemical metallization cells beneficially supports the functionality of the network. The voltage margin and energy consumption are analyzed for various crossbar array sizes. Moreover, a test setup to study those networks supported by measurements was developed and proof-of-concept results for a pre-programmed capacitive array are presented.

Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays

Memristive devices have been shown to have low leakage power, non-volatile storage capability and high storage density. In addition, by using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer functionalities such as arithmetic operations, which make them ideal target for in-memory computing. Multiplexers are useful circuits that are used in a wide variety of applications such as encoding-decoding, signal routing, data communications and data bus control. In this paper, we report the first study on implementation of multiplexers using 1S1R crossbar arrays. An efficient mapping of the multiplexers is presented, with logarithmic delay, in terms of number of control signals — n. Physics-based circuit simulations are performed to validate our approach.

Controllability of multi-level states in memristive device models using a transistor as current compliance during SET operation

Redox-based resistive switching devices are an emerging class of non-volatile ultra-scalable memory and logic devices. These devices offer complex internal device physics leading to rich dynamical behavior. Memristive device models are intended to reproduce the underlying redox-based resistive switching device behavior accurately to enable proper circuit simulations. A specific feature of resistively switching devices is the controllability of multi-level resistive states by using a current compliance during the SET operation. Here, we consider a one-transistor-one-resistive-switch circuit to study the multi-level capability of three different types of memristive models. The feasibility of current compliance induced multi-level resistance state control is a check for the accuracy of the memristive device model.