Deborah T. Marr

Hyperthreading technology in the netburst microarchitecture

Hyperthreading technology, which brings the concept of simultaneous multithreading to the Intel architecture, was first introduced on the Intel Xeon processor in early 2002 for the server market. In November 2002, Intel launched the technology on the Intel Pentium 4 at clock frequencies of 3.06 GHz and higher, making the technology widely available to the consumer market. This technology signals a new direction in microarchitecture development and fundamentally changes the cost-benefit tradeoffs of microarchitecture design choices. This article describes how the technology works, that is, how we make a single physical processor appear as multiple logical processors to operating systems and software. We highlight the additional structures and die area needed to implement the technology and discuss the fundamental ideas behind the technology and why we can get a 25-percent boost in performance from a technology that costs less than 5 percent in added die area. We illustrate the importance of choosing the right sharing policy for each shared resource by describing, examining, and comparing three different sharing policies: partitioned resources, threshold sharing, and full sharing. The choice of policy depends on the traffic pattern, complexity and size of the resource, potential deadlock/livelock scenarios, and other considerations. Finally, we show how this technology significantly improves performance on several relevant workloads.

Multiprocessor validation of the Pentium Pro microprocessor

The Pentium Pro microprocessor, the latest generation Intel Architecture processor, was designed to be used glue-lessly in multiprocessor (MP) systems. The processor and its associated chipset provide all the features that an MP system requires. Our challenge was to ensure that the Pentium Pro would be MP functional with the expected performance at first silicon. We accomplished this by developing a test methodology with self-checking test templates for validating the processors MP features, and using micro-benchmarks and high-level system models to verify MP hardware scalability.