Deepak Kachave

Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors

Abstract Radiation induced faults in digital systems have started gathering major attention in recent years due to increasing reliability concern for future technologies. For future technologies, multiple transient faults (MTF) originating from a single radiation hit are expected to occur more frequently. Further, due to continuous massive scaling in device geometry, a particle with moderate linear energy transfer (LET) values is expected to affect more than one module/device during striking. Additionally, incessant escalation in operating speed with evolution of technology has increased likelihood of multi-cycle transient (MCT) faults in digital circuits. This calls for novel solutions for concurrently tackling multi-cycle transient and multi-transient fault resiliency at a higher design abstraction level such as behavioral level. This paper proposes a novel approach for generating simultaneous multi-cycle transient and multiple transient fault resilient designs during high level synthesis (HLS) of application specific datapath processors using the framework of dual modular redundancy. Results of the proposed approach on benchmarks indicated generation of low cost MCT–MFT resilient designs during HLS within acceptable runtime.

Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis

Future technologies predict major reliability concern for digital systems due to growing impact of radiation based transient faults. Radiation strikes may produce upsets that last over several clock cycles and that can affect multiple functional units similarly (equivalently). This will be a problem in future as with the evolution of technology, the device geometry continues to shrink massively along with persistent escalation of operating speed. This calls for solutions that can confront the dual problem of multi-cycle and multiple transient faults at higher abstraction level (such as behavioural level) alongside considering lower level physical design information. A novel physically aware high level synthesis (HLS) methodology is presented in this paper, that solves the aforesaid problem by providing resilient designs against transient fault that extend over several control steps (clock cycles) and affect neighborhood functional units similarly, with minimal overhead and implementation runtime.

Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation

Device aging is a critical failure mechanism in nanoscale designs. Prolonged device degradation may result in failure. Delay degradation of a design depends on various factors such as threshold voltage, temperature, input vector pattern and so on. An attacker who is aware of this phenomenon may exploit by accelerating the performance degradation mechanism. This study proposes a novel reliability and threat analysis of negative bias temperature instability (NBTI) stress on digital signal processing (DSP) cores. The main contributions of this study are as follows: (a) identifying input vectors that cause maximum degradation of DSP cores due to NBTI stress, (b) analysing impact of NBTI stress for varying stress time on DSP core in terms of delay degradation and (c) analysing performance comparison of stress versus no-stress condition for various input vector samples.

Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis

Abstract Reusable Intellectual Property (IP) cores have become an obligatory mandate for combating conflicting objectives of maximizing design productivity and minimizing design cycle time. However, a reusable IP core needs protection against false (illegal) claim of ownership. In this paper, we propose a novel computational forensic engineering (CFE) based approach for resolving ownership problem of a reusable IP core generated during high level synthesis (HLS). Some of the major contributions of the proposed approach are as follows: (a) a novel methodology based on multiple design feature set (technology & control parameter independent) that is capable of resolving false claim of vendor ownership problem for an IP core generated during HLS (b) novel algorithms for extracting design features (from register transfer level (RTL) hardware description language (HDL)) of an IP core for determining the rightful owner (c) a novel signature free approach (with avg. runtime ∼ 2 s) that offers 0% hardware overhead and 0% degradation of IP functionality/quality compared to watermarking based IP ownership resolution techniques.