Dipanjan Roy

Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis

Intellectual Property (IP) core used in computing system-on-chip provides a unique blend of yielding enhanced design productivity with reduced design cycle time. However, leveraging benefits of IP core require protection against threats from both sellers and buyers perspective. This paper proposes a novel symmetrical IP core protection methodology that embeds a buyer fingerprint and seller watermark simultaneously during high level synthesis (HLS). The proposed work leverages major HLS steps to concurrently embed buyer fingerprint signature and seller watermark signature into a reusable IP core design. The proposed signature encoding for fingerprint and watermark is multi-variable in nature offering strong robustness, low embedding cost and low design overhead. Results on standard benchmarks indicated that the proposed symmetrical approach satisfies all the major protection features of a watermark and fingerprint such as strong robustness to both seller & buyer, low overhead, low runtime and low embedding cost. Further on comparison with baseline design (no protection), the proposed approach offers symmetrical protection (both buyer and seller) at less than 1% area overhead and less than 1.1% latency overhead. Additionally on comparison with a recent unsymmetrical approach, the proposed approach offers symmetrical protection (both buyer and seller) at 0% area overhead and less than 1.1% latency overhead. Proposed approach offers symmetrical protection at less than 1% area overhead.Proposed approach offers symmetrical protection at less than 1.1% latency overhead.Our work leverages HLS steps to embed vendor watermark and buyer fingerprint in IP design.

Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters]

Intellectual property (IP) chip sets are indispensable components of consumer electronics (CE) products, such as set-top boxes, digital televisions, digital video discs (DVDs), tablets, digital cameras, and audio-video receivers. They represent several years of investment, research, and development through expensive infrastructure. Watermarking in IP chip sets for the protection of CE devices against false claims of ownership, piracy, and counterfeiting has proven to be a promising solution. However, the design process of a watermarked (antipiracy-aware) IP chip set is complex, and no published work exists in the literature to introduce a formal design methodology. This column presents a formal design approach for antipiracy-aware IP chip sets for CE devices. Using robust multivariable signature-encoding methodology, decoded watermarking constraints are embedded into the formal architectural synthesis design steps of an IP chip set. Each step of the IP chip set design is lucidly introduced with the aid of a real-life benchmark from the domain of multimedia and digital signal processing.

Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools

Novel low cost scheduling driven watermarking methodology for CAD high level synthesis tools.Proposed watermarking methodology is based on a robust signature encoding that incurs zero hardware overhead and minimal delay overhead resulting into extremely low cost protection.Proposed watermark is capable to embed watermark in loop based control data flow graphs.Proposed watermark on comparison to similar approaches yields significant reduction of final embedding cost. This paper presents a novel low cost scheduling driven watermarking methodology for modern computer aided design (CAD) high level synthesis tools. The proposed watermarking algorithm is embedded in the scheduling module of a CAD high level synthesis (HLS) tool. The presented watermarking methodology is capable of reusable intellectual property (IP) core protection of control data flow graphs (CDFG) from a vendors perspective based on user provided resource constraint and loop unrolling factor as inputs. The proposed low cost robust watermarking embedded inside high level synthesis process protects an IP core against threats such as false claim of ownership and piracy. The proposed watermarking satisfies desirable properties such as covertness, robustness, low embedding cost and low complexity. Results of comparison indicated significant reduction in embedding cost through proposed technique than similar state of the art techniques.

Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters]

This article presents a novel framework for intellectual property (IP)- based lossless image compression used for camera systems. The proposed approach presents two subframeworks: a) two-dimensional (2-D) Haar wavelet transformation (HWT)- based forward pixel calculator IP for image compression and b) 2-D HWTbased inverse pixel calculator IP for image decompression. Each framework is capable of fully compressing and decompressing images through onestage computation during forward and inverse transformations. The proposed approach has been tested on images of critical data sets of medical applications [e.g., computed tomography (CT) images and satellite applications, including NASA images]. Results of compressed and decompressed images along with compression efficiency through the proposed framework for IP-based lossless image compression are also reported in this article.

Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper)

Abstract Internet of Things (IoT) powered by high level synthesis (HLS) provides huge opportunity of progress in the area of hardware design. However, the present era of hardware design involves globalization which poses security threat to the design integrators that rely on third party intellectual property (IP) cores for increasing design productivity at reduced design time. This paper presents for the first time in the literature, a low cost optimized hardware Trojan secured HLS approach for hardware (or application specific core) designs that is based on single or nested loop control data flow graphs (CDFG) applications. The paper presents multiple novel vendor allocation schemes (each with its own attribute of delay and area) as security constraint that yield Trojan secured schedules at behavioral level. Demonstration of the proposed approach on a nested loop case study asserts our proposed theory. Results on standard benchmarks indicate significant reduction in final solution cost compared to a similar approach.

DSP design protection in CE through algorithmic transformation based structural obfuscation

Structural obfuscation offers a means to effectively secure through obfuscation the contents of an intellectual property (IP) cores used in an electronic system-on-chip (SoC). In this work a novel structural obfuscation methodology for protecting a digital signal processor (DSP) IP core at the architectural synthesis design stage. The proposed approach specifically targets protection of IP cores that involve complex loops. Five different algorithmic level transformation techniques are employed: loop unrolling, loop invariant code motion, tree height reduction/increment, logic transformation and redundant operation removal. Each of these can yield camouflaged functionally equivalent designs. In addition, low cost obfuscated design is generated through proposed approach through the use of multi-stage algorithmic transformation and particle swarm optimization (PSO)-drive design space exploration (DSE). Results of proposed approach yielded an enhancement obfuscation of 22 % and reduction in obfuscated design cost of 55 % compared to similar prior art.