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Dive into the research topics where Deepak Kamalanathan is active.

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Featured researches published by Deepak Kamalanathan.


IEEE Transactions on Electron Devices | 2009

Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory

Ugo Russo; Deepak Kamalanathan; Daniele Ielmini; Andrea L. Lacaita; Michael N. Kozicki

Programmable metallization cell (PMC) memory, also known as conductive bridging RAM (CBRAM), is a resistive-switching memory based on non-volatile formation and dissolution of a conductive filament (CF) in a solid electrolyte. Although ease of fabrication, promising performance and multilevel (ML) capability make the PMC a possible candidate for post-flash non-volatile memories, further physical understanding is required to better assess its true potential. In this work, we investigate the kinetics involved in the programming operation (i.e., transition from the high resistance to the low resistance state), which occurs by voltage-driven ion migration and electrochemical deposition, and results in CF formation and growth. The main kinetic parameters controlling the programming operation are extracted from our electrical data. Also, CF growth and corresponding resistance decrease is shown to be controllable with reasonable accuracy in pulse mode by employing a variable load resistance which can dynamically control the programming kinetics. A semi-analytical physical model is shown to account for experimental data and allows for the engineering of fast and reliable ML programming in one transistor-one resistor (1T-1R) devices.


IEEE Electron Device Letters | 2009

Voltage-Driven On–Off Transition and Tradeoff With Program and Erase Current in Programmable Metallization Cell (PMC) Memory

Deepak Kamalanathan; Ugo Russo; Daniele Ielmini; Michael N. Kozicki

The transition from the on (low-resistance) to the off (high-resistance) state is studied for programmable metallization cell nonvolatile memories. The stability of the on state under stress voltage and the erase operation were characterized as a function of the initial resistance in the timescale from 100 mus to 100 s. The data suggest that the on-off transition is limited by voltage-driven ion hopping and that filaments with larger size, and hence lower resistance, are more stable. Finally, results are discussed with the aid of an analytical model for erase, which is also used to address the tradeoff between on-state stability and program/erase currents.


international electron devices meeting | 2013

Conductive-bridge memory (CBRAM) with excellent high-temperature retention

John R. Jameson; P. Blanchard; C. Cheng; John Dinh; Antonio R. Gallo; V. Gopalakrishnan; Chakravarthy Gopalan; B. Guichet; S. Hsu; Deepak Kamalanathan; David Kim; Foroozan Sarah Koushan; Ming Sang Kwan; K. Law; Derric Lewis; Y. Ma; V. McCaffrey; Sung-Wook Park; S. Puthenthermadam; E. Runnion; J. Sanchez; J. Shields; K. Tsai; A. Tysdal; D. Wang; R. Williams; Michael N. Kozicki; Janet Wang; Venkatesh P. Gopinath; Shane Hollmer

High-temperature data retention is a critical hurdle for the commercialization of emerging nonvolatile memories. For Conductive-Bridge RAM (CBRAM) [1], we discuss high-temperature retention in terms of the physics of quantum point contacts, and we report on a family of CBRAM cells that achieve excellent retention at temperatures exceeding 200°C.


Nanotechnology | 2011

Low voltage cycling of programmable metallization cell memory devices

Deepak Kamalanathan; A Akhavan; Michael N. Kozicki

Future nanoscale memory technologies must ultimately be able to operate at power supply voltages in the order of 0.6 V or less. We have demonstrated in this work that it is possible to utilize symmetric program-erase (P-E) cycling for Ag/Ag-Ge-S/W programmable metallization cell devices at voltages below 0.6 V and still maintain an OFF/ON resistance ratio well in excess or 10 over a wide range of program and erase currents (0.27, 1.6, 55 and 220 µA) as set by a series resistance. The distributions of resistance values for 10(4) P-E cycles indicate that the margins between the highest on- and lowest off-state resistances are sufficient for unambiguous differentiation in all but the lowest current case in which there is some overlap. In addition, there is no substantial change in switching speed for up to 1.5 × 10(6) P-E operations, the maximum number of cycles attempted in this study.


non-volatile memory technology symposium | 2007

ON State Stability of Programmable Metalization Cell (PMC) Memory

Deepak Kamalanathan; Sunil R. Baliga; Sarath Chandran Puthen Thermadam; Michael N. Kozicki

Programmable metallization cell (PMC) memory is a non-volatile memory technology that is based on the electrochemical growth of a metallic electrodeposit between two metal electrodes, one oxidizable and another electrochemically indifferent. Considerable research has already been done on the processing and the operation of these devices for a variety of materials and their performance has been shown to be promising. However, since the metallic features in PMC devices are grown rather than deposited and patterned, their behavior is expected to be different from that of a typical metallic wire. This work focuses on the characterization of these devices with respect to the durability of the ON state when stressed under various constant bias conditions. In general, negative bias (against the direction necessary for electrodeposition) leads to a slow increase in resistance whereas a positive bias results in a decrease in resistance.


non-volatile memory technology symposium | 2007

Solid Electrolyte Memory for Flexible Electronics

Sunil R. Baliga; Sarath Chandran Puthen Thermadam; Deepak Kamalanathan; David R. Allee; Michael N. Kozicki

Programmable metallization cell (PMC) memory is a non-volatile memory that stores data states as programming current-dependent resistance levels via growth or dissolution of a metallic electrodeposit between the two electrodes. PMC memory is extremely scalable and has shown good performance in terms of switching speed, retention and endurance. Another interesting property of this technology is that the devices are inherently flexible. In this paper, we demonstrate that this memory shows great potential for integration with flexible thin-film technology. We show that a PMC memory element can be controlled with a TFT switching element and that PMC devices can be fabricated on a flexible substrate and can continue to operate after being subjected to a high degree of bending.


Archive | 2014

Circuits and methods for placing programmable impedance memory elements in high impedance states

Deepak Kamalanathan; Juan Pablo Saenz Echeverry; Venkatesh P. Gopinath


Archive | 2013

Reverse program and erase cycling algorithms

David Kim; Deepak Kamalanathan; Foroozan Sarah Koushan


Archive | 2012

Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse

Deepak Kamalanathan; Foroozan Sarah Koushan; Juan Pablo Saenz Echeverry; John Dinh; Shane Hollmer; Michael N. Kozicki


Archive | 2013

Two terminal resistive access devices and methods of formation thereof

Deepak Kamalanathan; Foroozan Sarah Koushan

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A Akhavan

Arizona State University

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David R. Allee

Arizona State University

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