Deepak Pancholi

Smart bridge for memory core

Controlled Load Regulation and Improved Response Time of LDO with Adapative Current Distribution Mechanism

Self-Calibrating Relaxation Oscillator Based Clock Source

Statistical distribution based variable-bit error correction coding

Partial Feedback Mechanism in Voltage Regulators to Reduce Output Noise Coupling and DC Voltage Shift at Output

SUPPLY NOISE CURRENT CONTROL CIRCUIT IN BYPASS MODE

Auto-phase synchronization in delay locked loops

Controlled start-up of a linear voltage regulator where input supply voltage is higher than device operational voltage

Multiphase low lc buck regulator

PROCESS DETECTION CIRCUIT