Manuel Antonio d'Abreu

Impact of SoC power management techniques on verification and testing

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now and a key reason behind the shift towards multicore designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

From Specification to High-Volume Production

In order to meet the ever shrinking market window, the ability to ramp up chip volume production has become a significant challenge. This is due to simultaneous changes in technology, functionality, schedule, cost, etc. This article presents a set of requirements and a unique design flow developed by SanDisk to help meet on-time volume production.

Innovative practices session 2C: Memory test

Use of Nand Flash memory in storage devices is increasing at an exponential rate. As the technology feature size shrink, the reliability and endurance for the Nand device reduces. Currently Nand devices can have more than 258Gb cells. Testing such devices is not a trivial proposition. In this presentation we will discuss the failure modes for Nand flash, the test methods used and the challenges that we face.

Special session 8B: Embedded tutorial challenges in SSD

Nand Flash memory is the NVM technology of choice for solid storage devices. This tutorial will give an introduction to Flash Non Volatile Memory (NVM). Nand Flash will be discussed in detail. For completeness the tutorial will present Nor Flash as well as the roles for Nand and Nor Flash. The second part of the tutorial will be focused on issues related to reliability and endurance. Despite the advantages, NAND-based storage systems are not without challenges. For the next decade, Flash storage systems are expected to provide solutions with reduced product costs, further improved read/write performance at low power consumption, as well as better data integrity for the users. Growth in storage demand is phenomenal, which leads to the adoption of more aggressive technology to keep cost reasonable. This further leads to using smaller cells (∼10nm in geometry), as well as more bits/cell to improve storage density, as well as cost. Newer physical storage media requires closer system-level interaction to make the system feasible for reliable data storage solution. State-of-the-art error correcting coding (ECC) solution, as well as advanced digital signal processing (DSP) techniques, will be deployed to make future flash media reliable for all data storage customers. In addition, new system solutions will provide the NAND-based storage system longer endurance and better data retention.

NAND Flash memory: The driving technology in digital storage - Overview and challenges

Summary form only given. Nand Flash memory is the NVM technology of choice for solid storage devices. This talk will give an introduction to Flash Non Volatile Memory (NVM). For completeness the talk will also present Nor Flash as well as the roles for Nand and Nor Flash. The second part of the talk will be focused on issues related to reliability and endurance, and current solutions and future challenges. Despite the advantages, NAND-based storage systems are not without challenges. For the next decade, Flash storage systems are expected to provide solutions with reduced product costs, further improved read/write performance at low power consumption, as well as better data integrity for the users. Growth in storage demand is phenomenal, which leads to the adoption of more aggressive technology to keep cost reasonable. This further leads to using smaller cells (~10nm in geometry), as well as more bits/cell to improve storage density, as well as cost. Newer physical storage media requires closer system-level interaction to make the system feasible for reliable data storage solution. State-of-the-art error correcting coding (ECC) solution, as well as advanced memory signal processing (MSP) techniques, will be deployed to make future flash media reliable for all data storage customers. In addition, new system solutions will provide the NAND-based storage system longer endurance and better data retention. The talk will conclude with a discussion of challenges that require significant research.

Nand Flash Memory -- Product Trends, Technology Overview, and Technical Challenges

Flash technology role in storage is now mainstream. Nand Flash is the nonvolatile memory behind SSD, mobile computing devices and mobile appliances (such as phones and cameras). The cost reduction pace has imposed significant challenges to the architecture of the Nand device. Also product requirements related to performance and reliability have highlighted significant problems that have to be addressed. This talk will present an overview of the Flash technology. To put the presentation in the right perspective, an introduction to various products that use flash will be given along with technical challenges that each pose. Reliability is a major requirement that Flash memories must address. This talk will prevent a discussion on factors that affect reliability, how these are addressed and expected technical challenges in the next 2-4 years.

Panel: SoC power management implications on validation and testing

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.