Deepak Sharma

Reliability Impact of Chalcogenide-Structure Relaxation in Phase-Change Memory (PCM) Cells—Part I: Experimental Study

The phase-change memory (PCM) relies on the electrical properties of the chalcogenide materials to represent the stored bit of information. As a result, data stability depends on structural relaxation (SR) in the amorphous chalcogenide phase, which results in a temperature-accelerated time evolution of the electrical properties of the active material. Here, we address the time, temperature, and bias dependence of SR effects on the amorphous Ge2Sb2Te5 (GST) material used in PCM cells. Electrical measurements for increasing annealing time and temperature indicate that SR can be described by a defect annihilation process in the amorphous chalcogenide material. Finally, the stability of chalcogenide resistance as a function of the read conditions is discussed, for the purpose of reducing the impact of SR on the reliability of PCM devices.

Reliability Impact of Chalcogenide-Structure Relaxation in Phase-Change Memory (PCM) Cells—Part II: Physics-Based Modeling

Phase-change memory (PCM) cells are affected by structural relaxation (SR), which is the atomic-scale rearrangement of the amorphous phase of the chalcogenide material. Since SR affects the stability of electrical parameters of the PCM cell, such as resistance and threshold voltage, physics-based models for SR are necessary to analyze and predict the device reliability. This paper presents a physical model for SR in amorphous chalcogenide materials, linking the defect annihilation dynamics to the conduction behavior of the cell, hence to the electrical characteristics of the PCM cell. The model is able to predict the PCM cell characteristics as a function of annealing time, temperature, and read conditions.

Electrical transport and low-frequency noise in chemical vapor deposited single-layer MoS2 devices

We have studied temperature-dependent (77-300xa0K) electrical characteristics and low-frequency noise (LFN) in chemical vapor deposited (CVD) single-layer molybdenum disulfide (MoS2) based back-gated field-effect transistors (FETs). Electrical characterization and LFN measurements were conducted on MoS2 FETs with Al2O3 top-surface passivation. We also studied the effect of top-surface passivation etching on the electrical characteristics of the device. Significant decrease in channel current and transconductance was observed in these devices after the Al2O3 passivation etching. For passivated devices, the two-terminal resistance variation with temperature showed a good fit to the activation energy model, whereas for the etched devices the trend indicated a hopping transport mechanism. A significant increase in the normalized drain current noise power spectral density (PSD) was observed after the etching of the top passivation layer. The observed channel current noise was explained using a standard unified model incorporating carrier number fluctuation and correlated surface mobility fluctuation mechanisms. Detailed analysis of the gate-referred noise voltage PSD indicated the presence of different trapping states in passivated devices when compared to the etched devices. Etched devices showed weak temperature dependence of the channel current noise, whereas passivated devices exhibited near-linear temperature dependence.

Physical mechanism and temperature acceleration of relaxation effects in phase-change memory cells

The main reliability issues of phase change memory (PCM) cells are related to the metastable nature of the amorphous phase in the chalcogenide material. The amorphous phase spontaneously evolves during time by crystallization and structural relaxation, that is the short range ordering in the amorphous phase to minimize the defect concentration and free energy. Crystallization physics has been studied by almost 60 years, and application of the standard nucleation theory has been successfully applied to provide extrapolation methodologies for PCM reliability estimation. On the other hand, structural relaxation and its impact on carrier transport in the amorphous chalcogenide are not completely understood yet. The purpose of this paper is to study structural relaxation effects in PCM cells, focusing on a) the physical interpretation of the relaxation and b) the temperature acceleration of the phenomenon, which is essential to provide extrapolation techniques and analytical compact models for prediction of PCM reliability.

Transient effects of delay, switching and recovery in phase change memory (PCM) devices

Threshold switching effects play a critical role in phase change memory (PCM) devices, since they contribute to the programming (set/reset) times and may lead to unwanted disturbs during the read operation. This work presents a detailed characterization and modeling of transient effects of delay, switching and recovery in PCM devices, allowing to quantitatively evaluate the statistical impact of read disturb and the ultimate speed limitations to set/reset and program/verify loops.

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Threshold switching, i.e., the electrical transition from high to low resistivity in amorphous semiconductors, plays a major role in the program/erase processes of phase-change memory (PCM) devices. Understanding and designing materials and cell structures for optimum memory performance require that accurate models for threshold switching be developed, in both the steady-state and the transient regime. This work presents an experimental and modeling study of threshold switching in amorphous chalcogenide materials for PCM applications. The delay time for the onset of threshold switching from the application of an electrical pulse is explained based on 1/f fluctuations of the subthreshold current. A Monte Carlo model is developed for calculating the statistical distribution of delay times. The model can account for 1) the voltage dependence of the average delay time and 2) the statistical spread of the delay time for both rectangular and triangular voltage waveforms. The delay model is used for a reliability assessment of read disturb in PCM devices.

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We report detailed characterization of electrically-active deep-levels in doped Si nanowires (SiNWs) grown using catalyst-assisted vapor-liquid-solid (VLS) technique. Temperature-dependent low-frequency noise (LFN) spectroscopy was used to reveal the presence of generation-recombination related Lorentzian-type peaks along with 1/f-type noise in these NWs. In Ni-catalyzed SiNWs, the correlated LFN spectroscopy detected electrically active deep-levels with ionization energies of 0.42 eV for the n-type and 0.22 eV for the p-type SiNWs, respectively. In Au-catalyzed n- and p-type SiNWs, the energies of the deep-levels were estimated to be 0.44 and 0.38 eV, respectively. These values are in good agreement with the known ionization energies of deep-levels introduced by Ni and Au in Si. Associated trap concentrations and hole and electron capture cross sections were also estimated. This paper clearly indicated the presence of electrically active deep-levels associated with unintentional incorporation of catalyst atoms in the VLS-grown SiNWs.

Current Fluctuations in Phase-Change Memory Devices

Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20u2009nm thin lead zirconate titanate (PZT) ferroelectric film and 6u2009nm ultrathin high-κ titanium oxynitride (TiOxNy) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1u2009V under CVS of 0 to 15u2009V (5.76 MV/cm) at sweep voltage of ±5u2009V. Also, leakage current density (J) reduced from 5.57 to 1.94u2009μA/cm2 under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiOxNy buffer layer for Ferroelectric Random Access Memory. After programming at ±5u2009V, the high (CH) and low (CL) capacitances reliability remains distinguishable for 5000u2009s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiOxNy, r...

Detection of Deep-Levels in Doped Silicon Nanowires Using Low-Frequency Noise Spectroscopy

Leveraging nanoscale field-effect transistors (FETs) in integrated circuits depends heavily on its transfer characteristics and low-frequency noise (LFN) properties. Here, we report the transfer characteristics and LFN in FETs fabricated with molybdenum disulfide (MoS2) with different layer (L) counts. 4L to 6L devices showed highest ION-IOFF ratio (≈108) whereas LFN was maximum for 1L device with normalized power spectral density (PSD) ≈1.5 × 10−5u2009Hz−1. For devices with Lu2009≈u20096, PSD was minimum (≈2 × 10−8u2009Hz−1). Further, LFN for single and few layer devices satisfied carrier number fluctuation (CNF) model in both weak and strong accumulation regimes while thicker devices followed Hooges mobility fluctuation model in the weak accumulation regime and CNF model in strong accumulation regime, respectively. Transfer-characteristics and LFN experimental data are explained with the help of model incorporating Thomas-Fermi charge screening and inter-layer resistance coupling.

Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors

The Metal-Ferroelectric-Insulator-Semiconductor (MFIS) capacitors with thin 20 nm lead zirconate titanate (PZT) and titanium oxynitride (TiOxNy) buffer layer were fabricated by RF magnetron sputtering technique and characterized. TiOxNy as a buffer layer deposited for the first time for MFIS application at different thicknesses and fabricated structure was found to exhibit excellent electrical characteristics at 14 nm TiOxNy. Memory window of 0.4 V was found at low sweep voltage of ± 3 V which increases to 1.8 V at sweep voltage of ±14 V indicating multilevel data storage. Moreover the fabricated structure possesses low leakage current density of ∼4 µA/cm2 at 36 nm TiOxNy which increases to 12 µA/cm2 at 4 nm TiOxNy at 5 V, reasonable limit. Furthermore, the fabricated structure possesses outstanding data retention capability at 14 nm TiOxNy; the high and low capacitance becomes constant after few seconds and clearly distinguishable for 1h and 30 min. This shows that proposed MFIS structure is suitable for...