Dejan Radjen

A Receiver Architecture for Devices in Wireless Body Area Networks

A receiver architecture suitable for devices in wireless body area networks is presented. Such devices require minimum physical size and power consumption. To achieve this the receiver should, therefore, be fully integrated in state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology, and size and power consumption must be carefully considered at all levels of design. The chosen modulation is frequency shift keying, for which transmitters can be realized with high efficiency and low spurious emissions. A direct-conversion receiver architecture is used to achieve minimum power consumption and a modulation index equal to two is chosen, creating a midchannel notch in the modulated signal. A tailored demodulation structure has been designed to make the digital baseband compact and low power. To increase sensitivity it has been designed to interface with an analog decoder. Implementation in the analog domain minimizes the decoder power consumption. Antenna design and wave propagation are taken into account via simulations with phantoms. The 2.45-GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme has been designed, which is used both for system evaluation and for assisting system design choices. Receiver blocks have been fabricated in 65-nm CMOS, and a radio-frequency front-end and an analog-to-digital converter have been measured. Simulations of the complete baseband have been performed, investigating impairments due to 1/f noise, frequency and time offsets.

A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback

This paper presents a low-power multi-bit continuous-time ΔΣ modulator with a new approach to clock jitter reduction utilizing switched-capacitor-resistor techniques. The modulator features a 3rd order loop filter, implemented with active RC integrators, and 3-bit quantizer and feedback DACs. The ΔΣ modulator has been implemented in a 65nm CMOS process and tested. It achieves a peak SNDR of 70 dB in a 125 kHz signal bandwidth while consuming 380 µW. The combination of a high-order loop filter and multi-bit quantizer allows for a high resolution at a low sampling frequency of 4MHz, corresponding to an oversampling ratio of 16.

An Integrated 3-Level Fully Adjustable PWM Class-D Audio Amplifier in 0.35μm CMOS

A class-D audio amplifier utilizing a fully adjustable 3-level pulse width modulation (PWM) is presented. The amplifier is fully integrated in a 0.35 μm CMOS process, and is powered by a 3.3 V power supply. The system includes an internal fully adjustable triangle-wave oscillator, which is used to generate the PWM carrier. Delivering an output power of 300 mW is a differential bridge (7.5 cm pMOS, 3 cm nMOS), driving a 16 Ω load. The THD+N of the system is less than 0.2%, and the efficiency at 300 mW is 89%.

A low-power 2nd-order CT ΔΣ modulator with a single operational amplifier

This paper presents a multi-bit continuous-time ΔΣ modulator intended for ultra low power radios. The modulator features a 2nd order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution at a low oversampling ratio of 16. The ΔΣ modulator has been implemented in a 65nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth, while consuming 76 μW from a 800 mV power supply.

A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer

This paper presents a multi-bit continuous-time ΔΣ modulator intended for ultra-low-power radios. The modulator features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit asynchronous successive approximation register quantizer is used to achieve high resolution at a low oversampling ratio of 16. The ΔΣ modulator has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The modulator consumes 69 /μW from a 800 mV power supply.

A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio

A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.

A 0.13µm CMOS ΔΣ PLL FM transmitter

A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.