Henrik Sjöland

A filtering technique to lower LC oscillator phase noise

Test oscillators are implemented using the noise filtering schemes described: a top-biased and a tail-biased VCO for the 1GHz band, and a tail-biased VCO for the 2.2GHz band. These CMOS circuits are fabricated in the STMicroelectronics BiCMOS 6M process.

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.

Tail current noise suppression in RF CMOS VCOs

This paper presents the experimental results of two different techniques, inductive degeneration and capacitive filtering, for reducing the phase noise in tail-biased RF CMOS voltage-controlled oscillators (VCOs). Both techniques prevent the low-frequency tail current noise from being converted into phase noise. The techniques are applied to two distinct VCO designs, showing that the largest phase noise reduction (up to 6-7 dB at 3-MHz offset frequency from the carrier) is achieved via inductive degeneration. Capacitive filtering, however, also substantially reduces the phase noise at high offset frequencies and may therefore become a valid alternative to inductive degeneration, as discrete capacitors are of more common use than discrete inductors.

Improved switched tuning of differential CMOS VCOs

Varactors for continuous frequency tuning are typically used in LC-oscillators. However, they have some drawbacks for large tuning ranges, such as high tuning sensitivity causing high sensitivity to noise and disturbances on the control voltage. Furthermore, large metal-oxide-semiconductor (MOS) varactors have high conversion of harmless amplitude noise into harmful phase noise. To reduce these problems a small varactor can be used in combination with MOS-transistors that switch fixed capacitors in and out of the oscillator. The limitations due to the imperfect complementary metal-oxide-semiconductor (CMOS) switches are investigated, and an improved structure for use with the popular differential CMOS LC-oscillator is presented.

An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band

The difficulties encountered in matching an antenna to its optimal impedance are reduced with an adaptive 0.35-/spl mu/m CMOS circuit based on several switched shunt capacitors arranged in capacitor banks and on a few external series inductors. As high-quality inductors are difficult to obtain in CMOS, the inductors are placed either in an low-temperature cofired ceramic (LTCC) substrate or is a lumped component outside the core circuit. The circuits, presented here through a range of simulations, are optimized to function within the ISM 2.4-GHz band, but the general approach employed to improve matching can be used for other frequency bands as well. The circuits discussed provide a VSWR/spl les/2 match for every impedance with VSWR/spl les/5. There is a 1-dB power loss for a perfect 50 /spl Omega//spl rarr/50 /spl Omega/ transformation, a break-even point at VSWR=1.5, and a 3-dB increase in delivered power for VSWR= 4.3.

A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers

A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented. To reduce power consumption a biquad cell with simple architecture is used. A simple but efficient technique is also proposed to improve the linearity of the filter without increasing its power consumption. Coarse and fine tuning techniques are used to tune the cutoff frequency of the sixth-order Butterworth low-pass filter from 8.1 MHz to 13.5 MHz suitable for WLAN and WiMAX applications. The measurement results show an in-band IIP3 of + 22 dBm, an HD3 better than - 40 dB at 470 mVP input signal amplitude, and an input referred noise of 75 nV/√Hz at a power consumption of 4.35 mW from a 1-V supply. The differential filter occupies a chip area of 0.239 mm2 excluding pads.

A 2.2 GHz CMOS VCO with inductive degeneration noise suppression

A 1.4 V, 9 mA monolithic LC-tank voltage-controlled oscillator (VCO) fabricated in a standard 0.35 /spl mu/m CMOS process is presented. The VCO is tunable between 2.0 GHz and 2.37 GHz, and displays a phase noise between -140 dBc/Hz and -138 dBc/Hz at a 3 MHz offset frequency across the whole tuning range. This low phase noise is achieved through the use of an on-chip LC filter and an off-chip low frequency inductor, which totally remove the noise of the tail current source. The phase noise improvement due to the off-chip inductor is between 2 dB and 6 dB, increasing with higher oscillation frequencies.

A Receiver Architecture for Devices in Wireless Body Area Networks

A receiver architecture suitable for devices in wireless body area networks is presented. Such devices require minimum physical size and power consumption. To achieve this the receiver should, therefore, be fully integrated in state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology, and size and power consumption must be carefully considered at all levels of design. The chosen modulation is frequency shift keying, for which transmitters can be realized with high efficiency and low spurious emissions. A direct-conversion receiver architecture is used to achieve minimum power consumption and a modulation index equal to two is chosen, creating a midchannel notch in the modulated signal. A tailored demodulation structure has been designed to make the digital baseband compact and low power. To increase sensitivity it has been designed to interface with an analog decoder. Implementation in the analog domain minimizes the decoder power consumption. Antenna design and wave propagation are taken into account via simulations with phantoms. The 2.45-GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme has been designed, which is used both for system evaluation and for assisting system design choices. Receiver blocks have been fabricated in 65-nm CMOS, and a radio-frequency front-end and an analog-to-digital converter have been measured. Simulations of the complete baseband have been performed, investigating impairments due to 1/f noise, frequency and time offsets.

A 2 GHz merged CMOS LNA and mixer for WCDMA

A merged LNA and mixer with an on-chip VCO is fabricated in 0.35 /spl mu/m CMOS for a 2.1 GHz WCDMA receiver. The front-end consumes 8 mA from 2.7 V and gives NF of 3.2 dB, conversion gain of 24.2 dB, and input IP3 of -1.5 dBm. The VCO consumes 3 mA while achieving phase noise of -128.4 and -138.5 dBc/Hz at offsets of 5 and 15 MHz, respectively.

Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network

Switched capacitors are here investigated for use in reconfigurable matching networks, particularly for digital video broadcasting-handheld (DVB-H) frequencies. A 0.13-μm CMOS circuit is evaluated through both simulations and measurements. Source grounded nMOS transistors are used to switch high-quality metal capacitors located above metal layer 8. The quality factor and tuning range depend on frequency, switch voltage, capacitor size, and transistor width. There is a clear tradeoff between quality factor and tuning range, and measurements show quality factors above 50, 100, and 150 at tuning ranges of 3.9, 2.4, and 1.6, respectively. A reconfigurable matching network with the switched capacitors has been realized using external inductors and the measured matching domain for the DVB-H frequency band is shown. The total loss of the network is 1.0 dB, a result of the high-quality switched capacitors.